Methods for reducing soft errors in deep submicron integrated circuits

International Conference on Solid-State and Integrated Circuit Technology Proceedings

Volumn , Issue , 1998, Pages 516-519

  Zhang, Kevin ^a   Hareland, Scott ^a   Senyk, Borys ^a   Maiz, Jose ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

SOFT ERROR RATE (SER);

CMOS INTEGRATED CIRCUITS;

EID: 0032226711     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (4)