Scenarios of CMOS scaling

International Conference on Solid-State and Integrated Circuit Technology Proceedings

Volumn , Issue , 1998, Pages 12-16

  Wang, Kang L ^a   Lynch, William T ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0032226655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)