Low power 2-D DCT chip design using direct 2-D algorithm

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 145-150

  Chen, Liang Gee ^a   Jiu, Juing Ying ^a   Chang, Hao Chieh ^a   Lee, Yung Pin ^a   Ku, Chung Wei ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; COSINE TRANSFORMS; DIGITAL ARITHMETIC; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; ROM;

CRITICAL PATH SIMULATIONS; PARALLEL DISTRIBUTED ARITHMETIC ARCHITECTURES; SINGLE-POLY DOUBLE-METAL TECHNOLOGY;

MICROPROCESSOR CHIPS;

EID: 0032218694     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (5)