Pre-layout delay calculation specification for CMOS ASIC libraries

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 241-248

  Edamatsu, Hisakazu ^a   Homma, Katsumi ^a   Kakimoto, Masaru ^a   Koike, Yutaka ^a   Tabuchi, Kinya ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTERPOLATION; LOGIC DESIGN; MATHEMATICAL MODELS;

DELAY CALCULATION METHOD; LINEAR INTERPOLATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0032218670     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)