Compact parallel multipliers using the sign-generate method in FPGA

Microelectronics Journal

Volumn 29, Issue 11, 1998, Pages 827-831

  Tagzout, Samir ^a   Sahli, Leïla ^a  

^a Microlectron Lab Ctr D   (Algeria)

Author keywords

DSP; FPGA; Multiplication

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; TABLE LOOKUP;

CONSTANT COEFFICIENT MULTIPLIERS; PARALLEL MULTIPLIERS; SIGN GENERATE ALGORITHM;

MULTIPLYING CIRCUITS;

EID: 0032210056     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2692(97)00103-1     Document Type: Article

References (12)

1. P. Hayashi and T. Joshi, Design methodology for DSP ASIC. In International Conference on Signal Processing Applications & Technology ICSPAT'95, Boston, USA, October 1995, pp. 145-149.
2. K. Chapman, Constant coefficient multipliers, in International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, 1996, pp. 905-908.
3. G.R. Goslin, Using FPGAs in digital signal processing application, in International Conference on Signal Processing Applications & Technology ICSPAT'95, Boston, USA, October, 1995, pp. 145-149.
4. L. Mintzer, Large FFT's in a single FPGA, in International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, October, 1996, pp. 895-898.
5. P. Schulz, Embedding DSPs into FPGA-based structures of interconnection. In International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, October, 1996, pp. 949-952.
6. D.J. Ridge, R. Hamill, R.W. Craig, S.A. Farson and J.V. McCanny, Advanced DSP on FPGAs and CPLDs, in International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, October, 1996, pp. 934-938.
7. K. Chapman, KCM Solutions for the DSP market, in Workshop of the International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, October, 1996, p. 8.
8. B. Newgard, Signal processing with XILINX FPGAs, in Workshop of the International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, October, 1996.
9. K. Chapman, Fast integer multipliers using FPGAs XCELL Review, Quarterly Journal for Xilinx Programmable Logic Users 3rd quarter (1994) 28-31.
10. M. Annaratone and W.Z. Shen, The design of an LSI booth multiplier: nMOS vs. CMOS technology. Report of Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA, USA, 1984.
11. A.K. Oudjida, High speed and very compact two's complement serial/ parallel multipliers using Xilinx's FPGA, in International Conference on Signal Processing Applications & Technology ICSPAT'96, Boston, USA, 1996, pp. 924-928.
12. W.J. Stenzel, W.J. Kubitz, G.H. Garcia, A compact high-speed parallel multiplication scheme, IEEE Transact. Computation C-26 (10) (1977) 948-957.