-
1
-
-
0030081932
-
A true nonvolatile analog memory cell using coupling charge balancing
-
K.-H. Kim and K. Lee, "A true nonvolatile analog memory cell using coupling charge balancing," in ISSCC Dig. Tech. Papers, pp. 268-269, 1996.
-
(1996)
ISSCC Dig. Tech. Papers
, pp. 268-269
-
-
Kim, K.-H.1
Lee, K.2
-
2
-
-
0027694680
-
A floating-gate analog memory device for neural networks
-
Nov.
-
O. Fujita and Y. Amemiya, "A floating-gate analog memory device for neural networks," IEEE J. Solid-State Circuits, vol. 40, pp. 2029-2035, Nov. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.40
, pp. 2029-2035
-
-
Fujita, O.1
Amemiya, Y.2
-
3
-
-
0027879334
-
An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks
-
Dec.
-
H. Kosaka, T. Shibata, H. Ishii, and T. Ohmi, "An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks," IEDM Tech. Dig., pp. 623-626, Dec. 1993.
-
(1993)
IEDM Tech. Dig.
, pp. 623-626
-
-
Kosaka, H.1
Shibata, T.2
Ishii, H.3
Ohmi, T.4
-
4
-
-
0030084502
-
A 2.5 V 256-level nonvolatile analog storage device using EEPROM technology
-
H. V. Tran, T. Blyth, D. Sowards, L. Engh, B. S. Natarraj, T. Dunne, H. Wang, V. Sarin, T. Lam, H. Nazarian, and G. Hu, "A 2.5 V 256-level nonvolatile analog storage device using EEPROM technology," in ISSCC Dig. Tech. Papers, 1996, pp. 270-271.
-
(1996)
ISSCC Dig. Tech. Papers
, pp. 270-271
-
-
Tran, H.V.1
Blyth, T.2
Sowards, D.3
Engh, L.4
Natarraj, B.S.5
Dunne, T.6
Wang, H.7
Sarin, V.8
Lam, T.9
Nazarian, H.10
Hu, G.11
-
5
-
-
0024122968
-
An analog trimming circuit based on a floating-gate device
-
Dec.
-
E. Sackinger and W. Guggenbuhl, "An analog trimming circuit based on a floating-gate device," IEEE J. Solid-State Circuits, vol. 23, pp. 1437-1440, Dec. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1437-1440
-
-
Sackinger, E.1
Guggenbuhl, W.2
-
6
-
-
0024910918
-
Trimming analog circuits using floating-gate analog MOS memory
-
Dec.
-
L. R. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE J. Solid-State Circuits, vol. 24. pp. 1569-1575, Dec. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1569-1575
-
-
Carley, L.R.1
-
7
-
-
0028370929
-
A novel approach to controlled programming of tunnel-based floating-gate MOSFET's
-
Feb.
-
M. Lanzoni and B. Ricco, "A novel approach to controlled programming of tunnel-based floating-gate MOSFET's," IEEE J. Solid-State Circuits vol. 29, pp. 147-150, Feb. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 147-150
-
-
Lanzoni, M.1
Ricco, B.2
-
8
-
-
0029251968
-
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
-
Feb.
-
K. D. Suh, B. H. Suh, Y. H. Lim, J. K. Kim, Y. J. Choi, Y. N. Koh, S. S. Lee, S. C. Kwon, B. S. Choi, J. S. Yum, J. H. Choi, J. R. Kim, and H. K. Lim, "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 128-129.
-
(1995)
ISSCC Dig. Tech. Papers
, pp. 128-129
-
-
Suh, K.D.1
Suh, B.H.2
Lim, Y.H.3
Kim, J.K.4
Choi, Y.J.5
Koh, Y.N.6
Lee, S.S.7
Kwon, S.C.8
Choi, B.S.9
Yum, J.S.10
Choi, J.H.11
Kim, J.R.12
Lim, H.K.13
-
9
-
-
0001221385
-
EEPROM as analog storage device, with particular application in neural networks
-
June
-
C-K. Sin, A. Kramer, V. Hu, R. R. Chu, and P. K. Ko, "EEPROM as analog storage device, with particular application in neural networks," IEEE Trans. Electron Devices, vol. 39. pp. 1410-1419, June 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 1410-1419
-
-
Sin, C.-K.1
Kramer, A.2
Hu, V.3
Chu, R.R.4
Ko, P.K.5
-
10
-
-
0024737359
-
The EEPROM as an analog memory device
-
June
-
T.-C. Ong, P. K. Ko, and C. Hu, "The EEPROM as an analog memory device," IEEE Trans. Electron Devices, vol. 36, pp. 1840-1841, June 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.36
, pp. 1840-1841
-
-
Ong, T.-C.1
Ko, P.K.2
Hu, C.3
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