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Volumn 33, Issue 11, 1998, Pages 1758-1762

An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT MANUFACTURE;

EID: 0032204665     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726571     Document Type: Article
Times cited : (6)

References (10)
  • 1
    • 0030081932 scopus 로고    scopus 로고
    • A true nonvolatile analog memory cell using coupling charge balancing
    • K.-H. Kim and K. Lee, "A true nonvolatile analog memory cell using coupling charge balancing," in ISSCC Dig. Tech. Papers, pp. 268-269, 1996.
    • (1996) ISSCC Dig. Tech. Papers , pp. 268-269
    • Kim, K.-H.1    Lee, K.2
  • 2
    • 0027694680 scopus 로고
    • A floating-gate analog memory device for neural networks
    • Nov.
    • O. Fujita and Y. Amemiya, "A floating-gate analog memory device for neural networks," IEEE J. Solid-State Circuits, vol. 40, pp. 2029-2035, Nov. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.40 , pp. 2029-2035
    • Fujita, O.1    Amemiya, Y.2
  • 3
    • 0027879334 scopus 로고
    • An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks
    • Dec.
    • H. Kosaka, T. Shibata, H. Ishii, and T. Ohmi, "An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks," IEDM Tech. Dig., pp. 623-626, Dec. 1993.
    • (1993) IEDM Tech. Dig. , pp. 623-626
    • Kosaka, H.1    Shibata, T.2    Ishii, H.3    Ohmi, T.4
  • 5
    • 0024122968 scopus 로고
    • An analog trimming circuit based on a floating-gate device
    • Dec.
    • E. Sackinger and W. Guggenbuhl, "An analog trimming circuit based on a floating-gate device," IEEE J. Solid-State Circuits, vol. 23, pp. 1437-1440, Dec. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.23 , pp. 1437-1440
    • Sackinger, E.1    Guggenbuhl, W.2
  • 6
    • 0024910918 scopus 로고
    • Trimming analog circuits using floating-gate analog MOS memory
    • Dec.
    • L. R. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE J. Solid-State Circuits, vol. 24. pp. 1569-1575, Dec. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 1569-1575
    • Carley, L.R.1
  • 7
    • 0028370929 scopus 로고
    • A novel approach to controlled programming of tunnel-based floating-gate MOSFET's
    • Feb.
    • M. Lanzoni and B. Ricco, "A novel approach to controlled programming of tunnel-based floating-gate MOSFET's," IEEE J. Solid-State Circuits vol. 29, pp. 147-150, Feb. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 147-150
    • Lanzoni, M.1    Ricco, B.2
  • 9
    • 0001221385 scopus 로고
    • EEPROM as analog storage device, with particular application in neural networks
    • June
    • C-K. Sin, A. Kramer, V. Hu, R. R. Chu, and P. K. Ko, "EEPROM as analog storage device, with particular application in neural networks," IEEE Trans. Electron Devices, vol. 39. pp. 1410-1419, June 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1410-1419
    • Sin, C.-K.1    Kramer, A.2    Hu, V.3    Chu, R.R.4    Ko, P.K.5
  • 10
    • 0024737359 scopus 로고
    • The EEPROM as an analog memory device
    • June
    • T.-C. Ong, P. K. Ko, and C. Hu, "The EEPROM as an analog memory device," IEEE Trans. Electron Devices, vol. 36, pp. 1840-1841, June 1992.
    • (1992) IEEE Trans. Electron Devices , vol.36 , pp. 1840-1841
    • Ong, T.-C.1    Ko, P.K.2    Hu, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.