Scheduling and variable binding for improved testability in high level synthesis

Computers and Electrical Engineering

Volumn 24, Issue 6, 1998, Pages 441-461

  Ismaeel, Asad A ^a,b   Mathew, Rajan ^a   Bhatnagar, Rakesh ^a  

^a KUWAIT UNIVERSITY   (Kuwait)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Binding; Data flow graph; Design for testability; Scheduling

Indexed keywords

ALGORITHMS; CONTROLLABILITY; INTEGER PROGRAMMING; LINEAR PROGRAMMING; OBSERVABILITY;

COST BASED SCHEDULING SYSTEMS (CBSS); DATA FLOW GRAPH; REGISTER TRANSFER LEVEL (RTL);

ARTIFICIAL INTELLIGENCE;

EID: 0032203965     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0045-7906(98)00018-4     Document Type: Article

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