An analytical performance model for multistage interconnection networks with finite, infinite and zero length buffers

Performance Evaluation

Volumn 34, Issue 3, 1998, Pages 169-182

  Bouras, C ^a,b   Garofalakis, J ^a,b   Spirakis, P ^a,b   Triantafillou, V ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b University of Patras and Computer Technology Institute   (Greece)

Author keywords

Analytical models; Evaluation; Queueing theory models

Indexed keywords

APPROXIMATION THEORY; BENCHMARKING; BUFFER STORAGE; COMPUTER SIMULATION; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; QUEUEING THEORY;

MULTISTAGE INTERCONNECTION NETWORKS (MIN); STEADY-STATE DISTRIBUTIONS;

INTERCONNECTION NETWORKS;

EID: 0032202302     PISSN: 01665316     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0166-5316(98)00035-2     Document Type: Article

References (15)

1. C. Bouras, J. Garofalakis, P. Spirakis, V. Triantafillou, A general performance model for multistage interconnection networks, Euro-Par'97, August 25-29.
2. A. Gottlieb, R. Grishman, C.P. Kruscal, K.P. McAuliffe, L. Rudolph, M. Snir, The NYU Ultracomputer - Designing an MIMD shared memory parallel computer, IEEE Trans. Comput. C-322 (1983) 175-189.
3. G. Pfister, M.C. Brantley, D.A. George, S.L. Harvey, W.J. Kleinfelder, K.P. McAuliffe, E.A. Melton, V.A. Norton, J. Weiss, The IBM Research Parallel Processor Prototype (RP3): introduction and architecture, in: Proc. 1985 Int. Conf. Parallel Processing, pp. 764-771.
4. R. Rooholaminiight, Finding the right ATM switch for the market, IEEE J. Comput. (1994) 16-28.
5. C. Bouras, J. Garofalakis, P. Spirakis, V. Triantafillou, Queueing delays in buffered multistage interconnection networks, in: Proc. 1987 ACM Sigmetrics Conf., May 11-14, 1987, Banff, Alberta, Canada, pp. 111-121.
6. D.M. Dias, J.R. Jump, Analysis and simulation of buffered Delta Networks, IEEE Trans. Comput. C-30 (1981) 273-282.
7. J. Garofalakis, P. Spirakis, The performance of multistage interconnection networks with finite buffers, in: Proc. ACM SIGMETRICS Conf., 1990, short paper.
8. R.R. Koch, Increasing the size of a network by a constant factor can increase performance by more than a constant factor, in: IEEE Symp. Found. Comput. Sci. (FOCS 88), pp. 221-231.
9. C.P. Kruskal, M. Snir, The performance of multistage interconnection networks for multiprocessors, IEEE Trans. Comput. C-32 (1983) 1091-1098.
10. C.P. Kruskal, M. Snir, A. Weiss, The distribution of waiting times in closed multistage interconnection networks, IEEE Trans. Comput. 32 (1983) 1337-1352.
11. A. Merchant, A Markov chain approximation for the analysis of Banyan networks, in: Proc. ACM Sigmetrics Conf. on Measurement and Modelling of Computer Systems, 1991.
12. J.H. Patel, Performance of processor - memory interconnection for multiprocessors, IEEE Trans. Comput. C-30 (1981) 771-780.
13. R. Rehrmann, B. Monien, R. Luling, R. Diemann, On the communication throughput of buffered multistage interconnection networks, in: ACM SPAA'96, pp. 152-161.
14. G.F. Goke, G.J. Lipovski, Banyan networks for partitioning multiprocessor systems, in: Proc. 1st Ann. Symp. on Computer Architecture, 1973, pp. 21-28.
15. F.T. Leihton, Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, Morgan Kaufmann, Los altos, CA, 1992.