A 16 × 16 nonvolatile programmable analog vector-matrix multiplier

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 10, 1998, Pages 1502-1509

  Aslam Siddiqi, Amer ^a,b   Brockherde, Werner ^a,b   Hosticka, Bedrich J ^a,b  

^a IEEE   (Germany)

^b FRAUNHOFER INSTITUTE FOR MICROELECTRONIC CIRCUITS AND SYSTEMS   (Germany)

Author keywords

Analog memories; Analog multipliers; Erasable and programmable read only memory (EPROM)

Indexed keywords

ANALOG STORAGE; MATRIX ALGEBRA; MOSFET DEVICES; NONVOLATILE STORAGE; PROM; VECTORS;

ELECTRICALLY ERASABLE AND PROGRAMMABLE READ-ONLY MEMORIES (EEPROM);

MULTIPLYING CIRCUITS;

EID: 0032186579     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.720396     Document Type: Article

References (18)

1. F. J. Kub, K. K. Moon, I. A. Mack, and F. M. Long, "Programmable analog vector-matrix multipliers," IEEE J. Solid-State Circuits, vol. 25, pp. 207-214, Feb. 1990.
2. Y. Tsividis and S. Satyanarayana, "Analogue circuits for variablesynapse electronic neural networks," Electron. Lett., vol. 23, no. 24, pp. 1313-1314, Nov. 1987.
3. J.-I. Miyamoto, J.-I. Tsujimoto, N. Matsakawa, S. Morita, K. Shinada, H. Nozawa, and T. lizuka, "An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell," IEEE J. Solid-State Circuits, vol. SC-21, pp. 852-860, Oct. 1986.
4. C.-K. Sin, A. Kramer, V. Hu, R. R. Chu, and P. K. Ko, "EEPROM as an analog storage device, with particular applications in neural networks," IEEE Trans. Electron Devices, vol. 39, pp. 1410-1419, June 1992.
5. T. Blyth, S. Khan, and R. Simko, "A nonvolatile analog storage using EEPROM technology" in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 192-193.
6. M. Holler, S. Tam, H. Castro, and R. Benson, "An electrically trainable artificial neural network (ETANN) with 10240 'Floating Gate' synapses." in Proc. Int. Conf. Neural Networks, Washington, DC, June 18-22, 1989, pp. 11/191-11/196.
7. S. Kim, Y. C. Shin, N. C. R. Bogineni, and R. Sridhar, "A programmable analog CMOS synapse for neural networks," Analog Integrated Circuits Signal Process., vol. 2, no. 4, pp. 345-352, Nov. 1992.
8. L. R. Carley, "Trimming analog circuits using floating-gate analog MOS memory," IEEE J. Solid-State Circuits, vol. 24, pp. 1569-1574, Dec. 1989
9. A. Aslam, W. Brockherde, B. J. Hosticka, H. Vogt. and G. Zimmer. "A CMOS image sensor with combined analog nonvolatile storage capability," in Tech. Dig. IEDM, San Francisco, CA, Dec. 1996, pp. 923-926.
10. N. I. Khachab and M. Ismail, "MOS multiplier/divider cell for analogue VLSI," Electron. Lett., vol. 25, no. 23, pp. 1550-1552, Nov. 1989.
11. C. W. Park and S. B. Park. "New four-quadrant CMOS analogue multiplier," Electron. Lett., vol. 23, no. 24, pp. 1268-1270, Nov. 1987.
12. P. A. Shoemaker, G. L. Haviland, R. L. Shimabukuro, and I. Lagnado, "A simple CMOS analog four-qnadrant multiplier," Analog Integrated Circuits Signal Process., vol. 1, no. 2, pp. 107-117, Oct. 1991.
13. S.-C. Qin and R. L. Geiger, "A 5-V CMOS analog multiplier," IEEE J. Solid-State Circuits, vol. SC-22, pp. 1143-1146, Dec. 1987.
14. J. S. Pena-Finol and J. A. Connelly, "A MOS four-quadrant analog multiplier using the quarter-square technique," IEEE J. Solid-State Circuits, vol. SC-22. pp. 1064-1073, Dec. 1987.
15. H.-J. Song and C.-K. Kim, "AN MOS four-quadrant analog multiplier using simple two-input squaring circuits with Source followers," IEEE J. Solid-State Circuits, vol. 25, pp. 841-848, June 1990.
16. H. R. Mehrvarz and C. Y. Kwok, "A novel multi-input floating-gate MOS four-quadrant analog multiplier." IEEE J. Solid-State Circuits, vol. 31, pp. 1123-1131, Aug. 1996.
17. J. F. Schoeman and T.-H. Joubert, "Four quadrant analogue CMOS multiplier using capacitively coupled dual-gate transistors," Electron. Lett., vol. 32, no. 3, pp. 209-210, Feb. 1996.
18. Y.-Y. Chai and L. G. Johnson, "A 2 × 2 analog memory implemented with special layout injector." IEEE J. Solid-State Circuits, vol. 31, pp. 856-859, June 1996.