Fast tabular technique for fixed-polarity reed-muller logic with inherent parallel processes

International Journal of Electronics

Volumn 85, Issue 4, 1998, Pages 511-520

  Tan, E C ^a   Yang, H ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS; BOOLEAN ALGEBRA; COMPUTER CIRCUITS; DESIGN;

REED-MULLER LOGIC;

LOGIC CIRCUITS;

EID: 0032183930     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072198134067     Document Type: Article

References (14)

1. Almaini, A. E. A., 1994, Electronic Logic Systems (Englewood Cliffs, NJ: Prentice-Hall).
2. Almaini, A. E. A., and McKenzie, L., 1996, Tabular techniques for generating Kronecker expansions. Proceedings of the Institution of Electrical Engineers, Computers and Digital Techniques, 143, 205-212.
3. Almaini, A. E. A., Thomson, P., and Hanson, D., 1991, Tabular techniques for Reed-Muller logic. International Journal of Electronics, 70, 23-34.
4. Green, D. H., 1986, Modern Logic Design (Wokingham, UK: Addison-Wesley);
5. Green, D. H., 1987, Reed-Muller expansions of incompletely specifed functions. Proceedings of the Institution of Electrical Engineers, Comuters and Digital Techniques, 134, 228-236.
6. Harking, B., 1990, Efficient algorithm for canonical Reed-Muller expansions of Boolean functions. Proceedings of the Institution of Electrical Engineers, Computeers and Digital Techniques, 137, 366-370.
7. Lui, P. K., and Muzio, J. C., 1991, Boolean matrix transforms for the parity spectrum and minimisation of modulo-2 canonical expansions. Proceedings of the Institution of Electrical Engineers, Computers and Digital Techniques, 138, 411-417.
8. Miller, J. F., Luchian, H., Bradbeer, P. V. G., and Barclay, P. J. R. 1994, Using a genetic algorithm for optimizing fixed polarity Reed-Muller expansions of Boolean functions. International Journal of Electronics, 76, 601-609.
9. Miller, J. F., and Thomson, P., 1994, Highly efficient exhaustive search algorithm for optimizing canonical Reed-Muller expansions of Boolean functions. International Journal of Electronics, 76, 37-56.
10. Reddy, S. M., 1972, Easily testable realisations for logic functions. IEEE Transactions on Computers, 21, 1183-1188.
11. Sasao, T, and Besslich, P., 1990, On the complexity of mod-2 sum PLAs. IEEE Transactions on Computers, 39, 262-266.
12. Tran, A., 1987, Graphical method for the conversion of minterms to Reed-Muller coefficients and the minimisation of EX-OR switching functions. Proceedings of the Institution of Electrical Engineers, Computers and Digital Techniques, 134, 93-99;
13. Tran, A., 1989, Tri-state map for the minimisation of exclusive-OR switching functions. Proceedings of the Institution Electrical Engineers, Computers and Digital Technigues, 136, 16-21.
14. Wu, X., Chen, X., and Hurst, S. L., 1982, Mapping of Reed-Muller coefficients and the minimisation of EX-OR switching functions. Proceedings of the Institution of Electrical Engineers, Computers and Digital Techniques, 129, 15-20.