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Volumn 9, Issue 7, 1998, Pages 714-722

A simulation study of dispatch rules for reducing flow times in semiconductor wafer fabrication

Author keywords

Dispatch rules; Production scheduling; Semiconductor manufacturing management

Indexed keywords

COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DECISION THEORY; INTEGRATED CIRCUIT MANUFACTURE; PROCESS CONTROL; QUALITY ASSURANCE; SCHEDULING; STRATEGIC PLANNING;

EID: 0032183805     PISSN: 09537287     EISSN: 13665871     Source Type: Journal    
DOI: 10.1080/095372898233722     Document Type: Article
Times cited : (39)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.