Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

IEEE transactions on components, packaging and manufacturing technology. Part C. Manufacturing

Volumn 21, Issue 4, 1998, Pages 286-294

  Bock, Karlheinz ^a   Russ, Christian ^a   Badenes, Goncal ^a   Groeseneken, Guido ^a   Deferm, Ludo ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTROSTATICS; FAILURE ANALYSIS;

CHARGED DEVICE MODELS (CDM); ELECTROSTATIC DISCHARGES (ESD);

INTEGRATED CIRCUIT TESTING;

EID: 0032182618     PISSN: 10834400     EISSN: None     Source Type: None    
DOI: 10.1109/3476.739178     Document Type: Article

References (6)