On chip testing data converters using static parameters

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 3, 1998, Pages 409-419

  Arabi, Karim ^a,b   Kaminska, Bozena ^a,b   Sawan, Mohamad ^a,c  

^a IEEE   (United States)

^b Opmaxx Inc   (United States)

^c ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

Data converter; Fault detection analog circuits; Integrated circuit; Self test

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC NETWORK PARAMETERS; ERROR ANALYSIS; INTEGRATED CIRCUIT TESTING; NONLINEAR NETWORK ANALYSIS; SEMICONDUCTOR DEVICE STRUCTURES;

CHIP TESTING DATA CONVERTERS; DIFFERENTIAL NONLINEARITY (DNL) ERRORS; FAULT DETECTION ANALOG CIRCUITS; INTEGRAL NONLINEARITY (INL) ERRORS;

MICROPROCESSOR CHIPS;

EID: 0032165303     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711312     Document Type: Article

References (19)

1. B. Leung, "BiCMOS current cell and switch for digital-to-analog converters," IEEE J. Solid-State Circuits, vol. 28, pp. 68-71, Feb. 1993.
2. D. Wouter et al., "A self-calibration technique for monolithic high-resolution D/A converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
3. K. Arabi and B. Kaminska, "A new built-in self-test for digital-to-analog and analog-to-digital converters," in Proc. IEEE ICCAD, 1994, pp. 491-494.
4. J. W. Bandler and A. E. Salama, "Fault diagnosis of analog circuits," Proc. IEEE, vol. 73, pp. 1279-1325, Aug. 1985.
5. L. Milor et al., "Optimal test set design for analog circuits," in Proc. IEEE ICCAD, 1990, pp. 294-297.
6. M. Slamani and B. Kaminska, "Analog circuit fault diagnosis based on sensitivity computation and functional testing," in Proc. IEEE Design Test Computers, 1992, Mar. pp. 30-39.
7. M. Soma, "A design-for-test methodology for active analog filters," in Proc. IEEE Int. Test Conf., 1990, pp. 183-192.
8. M. J. Ohletz, "Hybrid built-in self-test (HBIST) structure for mixed analog/digital integrated circuits," in Proc. 2nd European Test Conf., 1991, pp. 307-316.
9. K. D. Wagner and T. W. Wiliams, "Design for testability of mixed signal integrated circuits," in Proc. IEEE Int. Test Conf., 1988, pp. 823-829.
10. S. Max, "Fast, accurate and complete ADC testing," in Proc. IEEE Int. Test Conf., 1989, pp. 598-640.
11. T. M. Souders and D. R. Flach, "An automated test set for high resolution analog-to-digital and digital-to-analog converters," IEEE Trans. Instrum. Meas., vol. IM-28, pp. 239-244, Dec. 1979.
12. J. R. Naylor, "Testing digital/analog and analog/digital converters" IEEE Trans. Circuits Syst., vol. CAS-25, pp. 526-538, July 1978.
13. E. Teraoca et al., "A built-in self-test for ADC and DAC in a single-chip speech CODEC," in Proc. IEEE Int. Test Conf., 1993, pp. 791-796.
14. H. J. Schouwenaars et al., "A low power stereo 16-bit CMOS D/A converter for digital audio," IEEE J. Solid-State Circuits, vol. 23, pp. 1290-1297, Dec. 1988.
15. A. Charoenrook and M. Soma, "Fault diagnosis of flash ADC using DNL test," in Proc. IEEE Int. Test Conf., 1993, pp. 680-685.
16. R. V. De Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. New York: Kluwer Acadamic, 1994, p. 475.
17. H. J. Schouwenaars et al., "A monolithic dual 16-Bit D/A converter," IEEE J. Solid-State Circuits, vol. SC-21, pp. 424-429, June 1986.
18. H. W. Singor and C. A. T. Salama, "A high performance CMOS compatible 5 1/2-bit current scaling D/A converter," Proc. Inst. Elec. Eng, 1989.
19. T. Miki, Y. Nakamura, et al., "An 80-MHz 8-bit CMOS D/A converter," IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, 1986.