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Volumn 6, Issue 3, 1998, Pages 475-483

Efficient VLSI for Lempel-Ziv compression in wireless data communication networks

Author keywords

Data compression; Lempel Ziv encoding; Low power; Systolic array

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; DATA COMPRESSION; ENCODING (SYMBOLS); INTEGRATED CIRCUIT LAYOUT; LOCAL AREA NETWORKS; MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; RANDOM ACCESS STORAGE; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 0032162921     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711318     Document Type: Article
Times cited : (12)

References (14)
  • 3
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  • 4
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  • 5
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    • ADLC and a pre-processor extension, BDLC, provide ultra fast compression for general-purpose and bit-mapped image data
    • D. J. Craft, "ADLC and a pre-processor extension, BDLC, provide ultra fast compression for general-purpose and bit-mapped image data," in Proc. Data Compression Conf., 1995, p. 440.
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    • Craft, D.J.1
  • 6
    • 0043183556 scopus 로고
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    • Feb.
    • T. Halfhill, "How safe is data compression," BYTE, pp. 56-74, Feb. 1994.
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    • Halfhill, T.1
  • 8
    • 0003859414 scopus 로고
    • Englewood Cliffs, NJ: Prentice-Hall
    • S. Y. Kung, VLSI Array Processors. Englewood Cliffs, NJ: Prentice-Hall, 1988.
    • (1988) VLSI Array Processors
    • Kung, S.Y.1
  • 10
    • 0027550112 scopus 로고
    • High-speed VLSI design for Lempel-Ziv-based data compression
    • Feb.
    • R. Ranganathan and S. Henriques, "High-speed VLSI design for Lempel-Ziv-based data compression," IEEE Trans. Circuits Syst., vol. 40, pp. 96-106, Feb. 1993.
    • (1993) IEEE Trans. Circuits Syst. , vol.40 , pp. 96-106
    • Ranganathan, R.1    Henriques, S.2
  • 11
    • 33747785550 scopus 로고
    • A massively parallel VLSI design for data compression using a compact dynamic dictionary
    • J. Storer, J. H. Reif, and T. Markas, "A massively parallel VLSI design for data compression using a compact dynamic dictionary," in Proc. IEEE Workshop VLSI Signal Processing, 1990, pp. 329-338.
    • (1990) Proc. IEEE Workshop VLSI Signal Processing , pp. 329-338
    • Storer, J.1    Reif, J.H.2    Markas, T.3
  • 12
    • 0017493286 scopus 로고
    • A universal algorithm for sequential data compression
    • J. Ziv and A. Lempel, "A universal algorithm for sequential data compression," IEEE Trans. Inform. Theory, vol. IT-23, no. 3, pp. 337-343, 1977.
    • (1977) IEEE Trans. Inform. Theory , vol.IT-23 , Issue.3 , pp. 337-343
    • Ziv, J.1    Lempel, A.2
  • 13
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    • Compression of individual sequence via variable rate coding
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  • 14
    • 3743123971 scopus 로고
    • A systolic architecture for sliding-window data compression
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    • Zito-Wolf, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.