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Volumn 13, Issue 5, 1998, Pages 283-288
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VLSI implementation of a strongly fault secure ALU
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Author keywords
Berger code prediction; Error detection; m out of n checkers; Self checking checkers; Strongly fault secure designs
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Indexed keywords
BUILT-IN SELF TEST;
CMOS INTEGRATED CIRCUITS;
COMPUTER AIDED LOGIC DESIGN;
DIGITAL ARITHMETIC;
ENCODING (SYMBOLS);
ERROR ANALYSIS;
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUIT TESTING;
OPTIMIZATION;
VLSI CIRCUITS;
BERGER CODES;
BIT PARALLEL OPERATIONS;
FAULT SECURE DESIGNS;
FAULT TOLERANT COMPUTER SYSTEMS;
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EID: 0032157806
PISSN: 02676192
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
Times cited : (1)
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References (10)
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