Stacked CSP (Chip Size Package) technology

Shapu Giho/Sharp Technical Journal

Volumn , Issue 71, 1998, Pages 58-63

  Fujita, Kazuya ^a   Kimura, Tomoshi ^a   Narai, Atsuya ^a   Sota, Yoshiki ^a   Miyata, Koji ^a   Matsune, Yuji ^a   Juso, Hiroyuki ^a   Fukui, Yasuki ^a   Yano, Yuji ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; LSI CIRCUITS; RANDOM ACCESS STORAGE;

STACKED CHIP SIZE PACKAGES (CSP);

MICROPROCESSOR CHIPS;

EID: 0032141296     PISSN: 02850362     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (3)

1. Y. Yamaji, K. Fujita et al. "Development of Highly Reliable CSP", ECTC, (1997).
2. SEMI Technology Symposium, (1997).