Theory and design of CMOS HSTL I/O pads

Hewlett-Packard Journal

Volumn 49, Issue 3, 1998, Pages 46-52

  Esch Jr , Gerald L ^a   Manley, Robert B ^a  

^a HP Integrated Circuit Business Division

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; IMPEDANCE MATCHING (ELECTRIC); INPUT OUTPUT PROGRAMS; INTEGRATED CIRCUIT LAYOUT;

HIGH-SPEED TRANSCEIVER LOGIC (HSTL); INTEGRATED CIRCUIT OUTPUT PAD DRIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 0032140530     PISSN: 00181153     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. G. Esch, Jr. and R. Manley, "HSTL CMOS I/O Pads for 200-MHz Data Rates." Proceedings of the 1996 Hewlett-Packard Design Technology Conference, pp. 51-58.
2. R. Canright, Jr., "The Impact of Driver Impedance upon Transmission Line Impedance," Proceedings of the 44th Electronic Components and Technology Conference, pp. 669-674.
3. HSTL (High-Speed Transceiver Logic), JEDEC Standard 16.3, Draft Revision 3, JEDEC Council, July 14, 1994.
4. R. Wilson, "JEDEC ready to approve very-high-speed I/O spec," Electronic Engineering Times, December 5, 1994, p. 1.