VLSI, MCM, and WSI: A design comparison

IEEE Design and Test of Computers

Volumn 15, Issue 3, 1998, Pages 28-34

  Swartzlander Jr , Earl E ^a,b,c,d,e  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b The University of Texas at Austin   (United States)

^c PURDUE UNIVERSITY   (United States)

^d UNIVERSITY OF COLORADO   (United States)

^e UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DIGITAL SIGNAL PROCESSING; ELECTRONICS PACKAGING; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; SEMICONDUCTING SILICON; SUBSTRATES; VLSI CIRCUITS; WSI CIRCUITS;

SUBSTRATE SIZE COST MODELS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032120612     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.706030     Document Type: Review

References (4)

1. K. Noguchi, S. Kawasaki, and Y. Akao, "New Generation RISC Microcomputer for Personal Information and Communication Equipment," Hitachi Review, Vol. 43, 1994, pp. 201-204.
2. K. Sato et al., "A System-Integrated ULSI Chip Containing Eleven 4MB RAMs, Six 64KB SRAMs and an 18K Gate Array," IEEE Int'l Solid-State Circuits Conf. Digest of Tech. Papers, IEEE Press, Piscataway, N.J., 1992, pp. 52, 53, and 241.
3. T. Nagai et al., "A 17ns 4Mb CMOS DRAM Using Direct Bit-Line Sensing Technique," IEEE Int'l Solid-State Circuits Conf. Digest of Tech. Papers, IEEE Press, Piscataway, N.J., 1991, pp. 58-59.
4. E.E. Swartzlander, Jr., VLSI Signal Processing Systems, Kluwer Academic, Boston, 1986, pp. 123-135.