Testability features of the AMD-K6 microprocessor

IEEE Design and Test of Computers

Volumn 15, Issue 3, 1998, Pages 64-69

  Fetherston, R Scott ^a,b,c,d   Shaik, Imtiaz P ^a,d,e,f,g,h   Ma, Siyad C ^a,d,i,j  

^a ADVANCED MICRO DEVICES   (United States)

^b Teledyne Systems   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IEEE   (United States)

^e JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY   (India)

^f ANNA UNIVERSITY   (India)

^g INDIAN SPACE RESEARCH ORGANISATION   (India)

^h RUTGERS UNIVERSITY   (United States)

ⁱ STANFORD UNIVERSITY   (United States)

^j KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

more..

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER DEBUGGING; COMPUTER HARDWARE; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT TESTING;

BUILT IN SELF TEST (BIST); DESIGN FOR TEST METHOD;

MICROPROCESSOR CHIPS;

EID: 0032119301     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.706035     Document Type: Review

References (7)

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7. DDQ Measurements," Proc. Int'l Test Conf., IEEE CS Press, 1992, pp. 778-787.