Design of a digital chaos circuit with nonlinear mapping function learning ability

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E81-A, Issue 6, 1998, Pages 1223-1230

  Eguch, Kei ^a   Inoue, Takahiro ^a   Tsuneda, Akio ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

Author keywords

Chaos circuits; Digital circuits; Discrete time circuits; Integrated circuits; Neiiro fuzzy circuits; Supervised learning

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUITS;

DIGITAL CHAOS CIRCUIT; NEURO-FUZZY CIRCUITS; NONLINEAR MAPPING FUNCTION LEARNING ABILITY;

DIGITAL CIRCUITS;

EID: 0032094498     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

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