Split-Lot Designs: Experiments for Multistage Batch Processes

Technometrics

Volumn 40, Issue 2, 1998, Pages 127-140

  Mee, Robert W ^a   Bates, Rodney L ^b  

^a UNIVERSITY OF TENNESSEE   (United States)

^b Federal Express   (United States)

Author keywords

Linear graph; Multiway split unit design; Orthogonal array; Split plot confounding; Splitb lock; Strip plot

Indexed keywords

GRAPH THEORY; SILICON WAFERS;

MULTISTAGE BATCH PROCESSES; MULTIWAY SPLIT UNIT DESIGN; SPLIT PLOT CONFOUNDING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0032075642     PISSN: 00401706     EISSN: 15372723     Source Type: Journal    
DOI: 10.1080/00401706.1998.10485195     Document Type: Article

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