A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 5, 1998, Pages 779-785

  Lee, Kyuchan ^b,c,d   Kim, Changhyun ^b,e,f   Yoon, Hongil ^b   Kim, Keum Yong ^a   Moon, Byung Sik ^b   Lee, Sang Bo ^b   Lee, Jung Hwa ^b   Kim, Nam Jong ^b   Cho, Soo In ^b  

^a IEEE

^b SAMSUNG Electronics   (South Korea)

^c Chungang University ^*

^d Chung Ang University   (South Korea)

^e Seoul National University   (South Korea)

^f UNIVERSITY OF MICHIGAN   (United States)

Author keywords

CMOS; Dynamic random access memory; Failure analysis; Gigabit; Testing

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; ELECTRON DEVICE TESTING; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; OPTIMIZATION; PERFORMANCE;

DYNAMIC RANDOM ACCESS MEMORY; GIGABIT; ON CHIP VOLTAGE SOURCES;

RANDOM ACCESS STORAGE;

EID: 0032072985     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.668993     Document Type: Article

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