1.04 GBd low EMI digital video interface system using small swing serial link technique

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 5, 1998, Pages 816-823

  Lee, Kyeongho ^a,b   Shin, Yeshik ^a,b   Kim, Sungjoon ^a,b   Jeong, Deog Kyoon ^a,b   Kim, Gyudong ^c   Kim, Bruce ^c   Da Costa, Victor ^c  

^a IEEE   (South Korea)

^b Seoul National University   (South Korea)

^c Silicon Image Inc   (United States)

Author keywords

Digital video interface; Electromagnetic interference; Flat panel system; Low voltage swing serial interface

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DATA COMMUNICATION SYSTEMS; DIGITAL IMAGE STORAGE; DISPLAY DEVICES; LIQUID CRYSTAL DISPLAYS; VIDEO SIGNAL PROCESSING;

DIGITAL VIDEO INTERFACE; ELECTROMAGNETIC INTERFERENCE; FLAT PANEL SYSTEM; LOW VOLTAGE SWING SERIAL INTERFACE;

PHASE LOCKED LOOPS;

EID: 0032070524     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.668999     Document Type: Article

References (6)

1. Y. Shin K. Lee, D.-K. Jeong, and D. D. Lee, "Transition-controlled digital encoding and signal transmission system," U.S. patent pending.
2. K. Lee, S. Kim, G. Ahn, and D.-K. Jeong, "CMOS serial link for fully duplexed data communication," IEEE J. Solid-State Circuits, vol. 30, pp. 353-363, Apr. 1995.
3. A. Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625 Gbps transceiver with 2X-oversampling and transmit signal pre-emphasis," in ISSCC 1997 Digest Tech. Papers, Feb., pp. 238-239.
4. S. Kim, K. Lee, D.-K. Jeong, D. D. Lee, and A. Nowatzyk, "An 800 Mbps multi-channel CMOS serial link with 3 X oversampling," in Proc. IEEE Custom Integrated Circuit Conf., 1995, pp. 451-454.
5. M. Bazes and R. Ashuri, "A novel CMOS digital clock and data decoder," IEEE J. Solid-State Circuits, vol. 27, pp. 1934-1940, Dec. 1992.
6. T. H. Hu and P. R. Gray, "A monolithic 480 M parallel AGC/decision/clock-recovery circuit in 1.2μm CMOS," IEEE J. Solid-State Circuits, vol. 28, pp. 1314-1320, Dec. 1993.