Neutral electron trap generation and hole trapping in thin oxides under electrostatic discharge stress

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 37, Issue 4 SUPPL. A, 1998, Pages 1671-1673

  Chim, Wai Kin ^a   Teh, Gim Leong ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

C V measurement; Electron trap; Electrostatic discharge; Hole trap; MOS capacitor; Neutral electron trap; Oxide reliability; Thin oxide; Transmission line pulsing

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC DISCHARGES; ELECTROSTATICS; MOS DEVICES; OXIDES; STRESSES; VOLTAGE MEASUREMENT;

ELECTROSTATIC DISCHARGE (ESD); HOLE TRAPPING; NEUTRAL ELECTRON TRAP GENERATION;

CAPACITORS;

EID: 0032048122     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.37.1671     Document Type: Article

References (8)

1. A. Amerasekera and C. Duvvury: ESD in Silicon Integrated Circuits (John Wiley & Sons, Chichester, 1995) p. 181.
2. S. Aur, A. Chatterjee and T. Polgreen: IEEE Trans. Electron Devices 35 (1988) 2189.
3. Y. Fong and C. Hu: Proc. 9th EOS/ESD Symp. (1987) p. 252.
4. T. Brozek and C. R. Viswanathan: Appl. Phys. Lett. 68 (1996) 1826.
5. T. J. Maloney and N. Khurana: Proc. of the 7th EOS/ESD Symp. (1985) p. 49.
6. N. Khurana, T. Maloney and W. Yeh: Proc. IEEE Int. Reliability Physics Symp. (1985) p. 212.
7. A. G. Revesz: IEEE Trans. Nucl. Sci. 18 (1971) 113.
8. F. J. Grunthaner, P. J. Grunthaner and J. Maserjian: IEEE Trans. Nucl. Sci. 29 (1982) 1462.