Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing

IEE Proceedings: Circuits, Devices and Systems

Volumn 145, Issue 2-5, 1998, Pages 132-134

  Lau, K T ^a   Lee, S T ^b   Ong, V K S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Analogue multiplier; VLSI signal processing

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; VLSI CIRCUITS;

ANALOG MULTIPLIER CELLS;

MULTIPLYING CIRCUITS;

EID: 0032046331     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19981846     Document Type: Article

References (11)

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