Molding challenges of LOC packages with large devices

IEEE transactions on components, packaging and manufacturing technology. Part C. Manufacturing

Volumn 21, Issue 2, 1998, Pages 142-147

  Paquet, Marie Claude ^a  

^a IBM CANADA LTD   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ENCAPSULATION; MICROPROCESSOR CHIPS; OPTIMIZATION; TRANSFER MOLDING;

LEAD ON CHIP (LOC) PACKAGES;

ELECTRONICS PACKAGING;

EID: 0032046305     PISSN: 10834400     EISSN: None     Source Type: Journal    
DOI: 10.1109/3476.681392     Document Type: Article

References (6)

1. EM Version 3.0 User's Guide 1995 E´TS E´TS
2. R. P. Judd N. A. Kheir An integrated computer-aided optimization system for process planning IFAC Workshop on Intelligent Manufacturing Systems 141 146 1992 Pergamon New York
3. M. Galopin T. M. Dao A knowledge based expert system for optimization of machining parameters Euro. Simulation Multiconf. 1991
4. O. Chacon M. C. Paquet P. Fortier M. Gauvin MFG Challenges overcome in LOC memory packages Proc. 2nd Int. Assembly Packag. Conf. (APCON'96) 1996 CA, Sunnyvale
5. L. T. Manzione Plastic Packaging of Microelectronic Devices. 1990 Van Nostrand Reinhold New York
6. S. A. David Arc welding procedure optimization Recent Trends in Welding Science and Technology 587 591 1990 ASM International OH, Metals Park