Optimization for thermal and electrical wiring for a flip-chip package using physical-neural network modeling

IEEE transactions on components, packaging and manufacturing technology. Part C. Manufacturing

Volumn 21, Issue 2, 1998, Pages 111-117

  Calmidi, V V ^a   Mahajan, R L ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC WIRING; ELECTRONICS PACKAGING; HEAT CONDUCTION; HEAT RESISTANCE; MATHEMATICAL MODELS; NEURAL NETWORKS; OPTIMIZATION;

THERMAL WIRING;

FLIP CHIP DEVICES;

EID: 0032046304     PISSN: 10834400     EISSN: None     Source Type: Journal    
DOI: 10.1109/3476.681386     Document Type: Article

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