-
1
-
-
0028419761
-
The role of VLSI in multimedia
-
Apr.
-
B. Ackland, "The role of VLSI in multimedia." IEEE J. Solid St. Ccts. 29, pp. 381-388, Apr. 1994.
-
(1994)
IEEE J. Solid St. Ccts.
, vol.29
, pp. 381-388
-
-
Ackland, B.1
-
3
-
-
0025457801
-
Source coding of speech and video signals
-
July
-
S. Singhal, D. L. Gall, and C. T. Chen, "Source coding of speech and video signals." Proc. IEEE 78, pp. 1233-1249, July 1990.
-
(1990)
Proc. IEEE
, vol.78
, pp. 1233-1249
-
-
Singhal, S.1
Gall, D.L.2
Chen, C.T.3
-
4
-
-
0021412027
-
Vector quantization
-
Apr.
-
R. M. Gray, "Vector quantization." IEEE ASSP Mag. pp. 4-29, Apr. 1984.
-
(1984)
IEEE ASSP Mag.
, pp. 4-29
-
-
Gray, R.M.1
-
5
-
-
0025489075
-
The self-organizing map
-
Sept.
-
T. Kohonen, "The self-organizing map." Proc. IEEE 78, pp. 1464-1480, Sept. 1990.
-
(1990)
Proc. IEEE
, vol.78
, pp. 1464-1480
-
-
Kohonen, T.1
-
7
-
-
0015749493
-
Self organization of orientation selective cells in striate cortex
-
C. von der Malsburg, "Self organization of orientation selective cells in striate cortex." Kybernetik 14, pp. 85-100, 1973.
-
(1973)
Kybernetik
, vol.14
, pp. 85-100
-
-
Von Der Malsburg, C.1
-
8
-
-
0017166860
-
How patterned neural connections can be set up by self organization
-
D. J. Willshaw and C. von der Malsburg, "How patterned neural connections can be set up by self organization." Proc. Royal Soc. London B 194, pp. 431-445, 1976.
-
(1976)
Proc. Royal Soc. London B
, vol.194
, pp. 431-445
-
-
Willshaw, D.J.1
Von Der Malsburg, C.2
-
9
-
-
0002370343
-
Network self-organization
-
S. F. Zornetzer, J. L. Davis, and C. Lau, editors, Academic Press: San Diego
-
C. von der Malsburg, "Network self-organization," in An Introduction to Neural and Electronic Networks, S. F. Zornetzer, J. L. Davis, and C. Lau, editors, Academic Press: San Diego, 1990.
-
(1990)
An Introduction to Neural and Electronic Networks
-
-
Von Der Malsburg, C.1
-
10
-
-
0016758101
-
Cognitron: A self-organizing multilayered neural network
-
K. Fukushima, "Cognitron: A self-organizing multilayered neural network." Biol. Cybern. 20, pp. 121-136, 1975.
-
(1975)
Biol. Cybern.
, vol.20
, pp. 121-136
-
-
Fukushima, K.1
-
11
-
-
0020970740
-
Neocognitron: A neural network model for a mechanism of visual pattern recognition
-
K. Fukushima, "Neocognitron: A neural network model for a mechanism of visual pattern recognition." IEEE Trans. Syst., Man and Cybern. 13, pp. 826-834, 1983.
-
(1983)
IEEE Trans. Syst., Man and Cybern.
, vol.13
, pp. 826-834
-
-
Fukushima, K.1
-
12
-
-
0017120827
-
Adaptive pattern classification and universal receding: I. Parallel development and coding of neural feature detectors
-
S. Grossberg, "Adaptive pattern classification and universal receding: I. Parallel development and coding of neural feature detectors." Biol. Cybernetics 23, pp. 121-134, 1976.
-
(1976)
Biol. Cybernetics
, vol.23
, pp. 121-134
-
-
Grossberg, S.1
-
13
-
-
5244352553
-
Competitive learning: From interactive activation to adaptive resonance
-
S. Grossberg, "Competitive learning: From interactive activation to adaptive resonance." Cognitive Science 11, pp. 23-63, 1987.
-
(1987)
Cognitive Science
, vol.11
, pp. 23-63
-
-
Grossberg, S.1
-
14
-
-
0017713690
-
Dynamics of pattern formation in lateral-inhibition type neural fields
-
S. A. Amari, "Dynamics of pattern formation in lateral-inhibition type neural fields." Biol. Cybern. 27, pp. 77-87, 1977.
-
(1977)
Biol. Cybern.
, vol.27
, pp. 77-87
-
-
Amari, S.A.1
-
15
-
-
0020068152
-
Self-organized formation of topologically correct feature maps
-
T. Kohonen, "Self-organized formation of topologically correct feature maps." Biol. Cybern. 43, pp. 59-69, 1982.
-
(1982)
Biol. Cybern.
, vol.43
, pp. 59-69
-
-
Kohonen, T.1
-
17
-
-
0002656190
-
Feature discovery by competitive learning
-
D. E. Rumelhart and D. Zipser, "Feature discovery by competitive learning." Cognitive Science 9, pp. 75-112, 1985.
-
(1985)
Cognitive Science
, vol.9
, pp. 75-112
-
-
Rumelhart, D.E.1
Zipser, D.2
-
19
-
-
0010578403
-
Digital neurochip design
-
K. W. Przytula and V K. Prasanna, editors, Prentice Hall: Englewood Cliffs, Chap. 8
-
J. Burr, "Digital neurochip design," in Parallel Digital Implementations of Neural Networks, K. W. Przytula and V K. Prasanna, editors, Prentice Hall: Englewood Cliffs, 1993, Chap. 8, pp. 223-281.
-
(1993)
Parallel Digital Implementations of Neural Networks
, pp. 223-281
-
-
Burr, J.1
-
20
-
-
0028425063
-
Quantization effects in digitally behaving circuit implementations of Kohonen networks
-
May
-
P. Thiran, V. Peiris, P. Heim, and B. Hochet, "Quantization effects in digitally behaving circuit implementations of Kohonen networks." IEEE Trans. NNs 5, pp. 450-458, May 1994.
-
(1994)
IEEE Trans. NNs
, vol.5
, pp. 450-458
-
-
Thiran, P.1
Peiris, V.2
Heim, P.3
Hochet, B.4
-
21
-
-
0026116469
-
Pulse-stream VLSI neural networks mixing analog and digital techniques
-
Mar.
-
A. F. Murray, D. Del Corso, and L. Tarassenko, "Pulse-stream VLSI neural networks mixing analog and digital techniques." IEEE Trans. on Neural Networks 2, pp. 193-204, Mar. 1991.
-
(1991)
IEEE Trans. on Neural Networks
, vol.2
, pp. 193-204
-
-
Murray, A.F.1
Del Corso, D.2
Tarassenko, L.3
-
22
-
-
67649119451
-
A precise four quadrant multiplier with subnanosecond response
-
B. Gilbert, "A precise four quadrant multiplier with subnanosecond response." IEEE J. Solid State Ccts. SC-3, p. 365, 1968.
-
(1968)
IEEE J. Solid State Ccts.
, vol.SC-3
, pp. 365
-
-
Gilbert, B.1
-
23
-
-
0025387945
-
Programmable analog vector-matrix multipliers
-
Feb
-
F. J. Kub, K. K. Moon, I. A. Mack, and F. M. Long, "Programmable analog vector-matrix multipliers." IEEE J. Solid St. Ccts. 25, pp. 207-214, Feb. 1990.
-
(1990)
IEEE J. Solid St. Ccts.
, vol.25
, pp. 207-214
-
-
Kub, F.J.1
Moon, K.K.2
Mack, I.A.3
Long, F.M.4
-
24
-
-
0026386918
-
CMOS implementation of analog Hebbian synaptic learning circuits
-
Seattle, WA
-
C. R. Schneider and H. C. Card, "CMOS implementation of analog Hebbian synaptic learning circuits," in Proc Int. Joint Conf. on Neural Networks, Seattle, WA, 1991, Vol. 1, pp. 437-442.
-
(1991)
Proc Int. Joint Conf. on Neural Networks
, vol.1
, pp. 437-442
-
-
Schneider, C.R.1
Card, H.C.2
-
25
-
-
0027641150
-
Analog CMOS deterministic Boltzmann circuits
-
Aug.
-
C. R. Schneider and H. C. Card, "Analog CMOS deterministic Boltzmann circuits." IEEE J. Solid St. Ccts. 28, pp. 907-914, Aug. 1993.
-
(1993)
IEEE J. Solid St. Ccts.
, vol.28
, pp. 907-914
-
-
Schneider, C.R.1
Card, H.C.2
-
26
-
-
0028751787
-
Learning capacitive weights in analog CMOS neural networks
-
H. C. Card, C. R. Schneider, and R. S. Schneider, "Learning capacitive weights in analog CMOS neural networks." J. VLSI Sign. Proc. 8, pp. 209-225, 1994.
-
(1994)
J. VLSI Sign. Proc.
, vol.8
, pp. 209-225
-
-
Card, H.C.1
Schneider, C.R.2
Schneider, R.S.3
-
27
-
-
0024647086
-
A programmable neural network chip
-
Apr
-
D. B. Schwartz, R. E. Howard, and W. E. Hubbard, "A programmable neural network chip." J. Solid St. Ccts. 24, pp. 313-319, Apr 1989.
-
(1989)
J. Solid St. Ccts.
, vol.24
, pp. 313-319
-
-
Schwartz, D.B.1
Howard, R.E.2
Hubbard, W.E.3
-
28
-
-
2342580599
-
Analog storage of adjustable synaptic weights
-
U. Ramacher and U. Ruckert, editors, Kluwer: Boston
-
E. Vittoz, H. Oguey, M. A. Maher, O. Nys, E. Dijkstra, and M. Chevroulet, "Analog storage of adjustable synaptic weights," in VLSI Design of Neural Networks, U. Ramacher and U. Ruckert, editors, Kluwer: Boston, 1991, pp. 47-63.
-
(1991)
VLSI Design of Neural Networks
, pp. 47-63
-
-
Vittoz, E.1
Oguey, H.2
Maher, M.A.3
Nys, O.4
Dijkstra, E.5
Chevroulet, M.6
-
29
-
-
0011716759
-
Analog memories for VLSI neurocomputing
-
E. Sanchez-Sinencio and C. Lau, editors
-
Y. Horio and S. Nakamura, "Analog memories for VLSI neurocomputing," in Artificial Neural Networks: Paradigms, Applications, and Hardware Implementations, E. Sanchez-Sinencio and C. Lau, editors, 1992, pp. 344-363.
-
(1992)
Artificial Neural Networks: Paradigms, Applications, and Hardware Implementations
, pp. 344-363
-
-
Horio, Y.1
Nakamura, S.2
-
30
-
-
0026123818
-
Implementation of a learning Kohonen neuron based on a new multilevel storage technique
-
Mar.
-
B. Hochet, V. Peiris, S. Abdo, and M. J. Declercq, "Implementation of a learning Kohonen neuron based on a new multilevel storage technique." IEEE J. Solid St. Ccts. 26, pp. 262-267, Mar. 1991.
-
(1991)
IEEE J. Solid St. Ccts.
, vol.26
, pp. 262-267
-
-
Hochet, B.1
Peiris, V.2
Abdo, S.3
Declercq, M.J.4
-
31
-
-
0026188495
-
Error correction technique for multivalued MOS memory
-
E. K. F. Lee and P. G. Gulak, "Error correction technique for multivalued MOS memory." Elect. Lett. 27, pp. 1321-1323, 1991.
-
(1991)
Elect. Lett.
, vol.27
, pp. 1321-1323
-
-
Lee, E.K.F.1
Gulak, P.G.2
-
32
-
-
0027107031
-
Field programmable analogue array based on MOSFET transconductors
-
E. K. F. Lee and P. G. Gulak, "Field programmable analogue array based on MOSFET transconductors." Elect. Lett. 28, pp. 28-29, 1992.
-
(1992)
Elect. Lett.
, vol.28
, pp. 28-29
-
-
Lee, E.K.F.1
Gulak, P.G.2
-
33
-
-
0026219838
-
Self refreshing analogue memory cell for variable synaptic weights
-
R. Castello, D. D. Caviglia, M. Franciotta, and F. Montecchi, "Self refreshing analogue memory cell for variable synaptic weights." Elect. Lett. 27, pp. 1871-1873, 1991.
-
(1991)
Elect. Lett.
, vol.27
, pp. 1871-1873
-
-
Castello, R.1
Caviglia, D.D.2
Franciotta, M.3
Montecchi, F.4
-
34
-
-
2342528926
-
Analog ANN weight storage elements with on-chip learning capabilities using switched capacitors
-
Halifax, Canada, Oct.
-
E. El-Masry and B. Maundy, "Analog ANN weight storage elements with on-chip learning capabilities using switched capacitors," in Proc. Can. Conf. on VLSI, Halifax, Canada, Oct. 1992, pp. 220-227.
-
(1992)
Proc. Can. Conf. on VLSI
, pp. 220-227
-
-
El-Masry, E.1
Maundy, B.2
-
35
-
-
0026987728
-
A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses
-
Y. Arima, M. Murasaki, T. Yamada, A. Maeda, and H. Shinohara, "A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses." IEEE J. Solid St. Ccts. 27, pp. 1854-1861, 1992.
-
(1992)
IEEE J. Solid St. Ccts.
, vol.27
, pp. 1854-1861
-
-
Arima, Y.1
Murasaki, M.2
Yamada, T.3
Maeda, A.4
Shinohara, H.5
-
36
-
-
0026260029
-
A 336-neuron, 28K synapse, self-learning neural network chip with branch-neuron-unit architecture
-
Nov.
-
Y. Arima, K. Mashiko, K. Okada, T. Yamada, A. Maeda, H. Notani, H. Kondoh, and S. Kayano, "A 336-neuron, 28K synapse, self-learning neural network chip with branch-neuron-unit architecture." IEEE J. Solid St. Ccts. 26, pp. 1637-1644, Nov. 1991.
-
(1991)
IEEE J. Solid St. Ccts.
, vol.26
, pp. 1637-1644
-
-
Arima, Y.1
Mashiko, K.2
Okada, K.3
Yamada, T.4
Maeda, A.5
Notani, H.6
Kondoh, H.7
Kayano, S.8
-
37
-
-
0026202292
-
Analogue noise enhanced learning in neural network circuits
-
A. F. Murray, "Analogue noise enhanced learning in neural network circuits." Elect. Lett. 27, pp. 1546-1548, 1991.
-
(1991)
Elect. Lett.
, vol.27
, pp. 1546-1548
-
-
Murray, A.F.1
-
38
-
-
0027053530
-
Probabilistic rounding in neural network learning with limited precision
-
M. Hohfeld and S. E. Fahlman, "Probabilistic rounding in neural network learning with limited precision." Neurocomputing 4, pp. 291-299, 1992.
-
(1992)
Neurocomputing
, vol.4
, pp. 291-299
-
-
Hohfeld, M.1
Fahlman, S.E.2
-
39
-
-
0027791987
-
Analog circuits for relaxation networks
-
Dec.
-
H. C. Card, "Analog circuits for relaxation networks." Int. J. Neural Syst. 4, pp. 359-379, Dec. 1993.
-
(1993)
Int. J. Neural Syst.
, vol.4
, pp. 359-379
-
-
Card, H.C.1
-
40
-
-
0029378529
-
Tolerance to analog hardware of on-chip learning in backpropagation networks
-
Sept.
-
B. K. Dolenko and H. C. Card, "Tolerance to analog hardware of on-chip learning in backpropagation networks." IEEE Trans. Neural Networks 6, pp. 1045-1052, Sept. 1995.
-
(1995)
IEEE Trans. Neural Networks
, vol.6
, pp. 1045-1052
-
-
Dolenko, B.K.1
Card, H.C.2
-
41
-
-
0026712578
-
Weight perturbation: An optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks
-
M. Jabri and B. Flower, "Weight perturbation: An optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks." IEEE Trans. Neural Networks 3, pp. 154-157, 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 154-157
-
-
Jabri, M.1
Flower, B.2
-
42
-
-
0000260241
-
A parallel gradient descent method for learning in analog VLSI neural networks
-
S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann
-
J. Alspector, R. Meir, B. Yuhas, A. Jayakumar, and D. Lippe, "A parallel gradient descent method for learning in analog VLSI neural networks," in Adv. Neural Info. Proc. Syst. 5, S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann, 1993, pp. 836-844.
-
(1993)
Adv. Neural Info. Proc. Syst. 5
, pp. 836-844
-
-
Alspector, J.1
Meir, R.2
Yuhas, B.3
Jayakumar, A.4
Lippe, D.5
-
43
-
-
0025792933
-
A VLSI efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks
-
Jan.
-
J. Alspector, J. W. Gannett, S. Haber, M. B. Parker, and R. Chu, "A VLSI efficient technique for generating multiple uncorrelated noise sources and its application to stochastic neural networks." IEEE Trans. Circuits and Syst. 38, p. 109, Jan. 1991.
-
(1991)
IEEE Trans. Circuits and Syst.
, vol.38
, pp. 109
-
-
Alspector, J.1
Gannett, J.W.2
Haber, S.3
Parker, M.B.4
Chu, R.5
-
44
-
-
0000610830
-
Summed-weight neuron perturbation: An O(N) improvement over weight perturbation
-
S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann
-
B. Flower and M. Jabri, "Summed-weight neuron perturbation: An O(N) improvement over weight perturbation," in Adv. Neural Info. Proc. Syst. 5, S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann, 1993, pp. 244-251.
-
(1993)
Adv. Neural Info. Proc. Syst. 5
, pp. 244-251
-
-
Flower, B.1
Jabri, M.2
-
45
-
-
0001149625
-
A Fast stochastic error-descent algorithm for supervised learning and optimization
-
Denver
-
G. Cauwenberghs, "A Fast stochastic error-descent algorithm for supervised learning and optimization," in Proc. NIPS-5, Denver, 1992.
-
(1992)
Proc. NIPS-5
-
-
Cauwenberghs, G.1
-
47
-
-
0037809101
-
Analog VLSI implementation of gradient descent
-
S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann
-
D. B. Kirk, D. Kerns, K. Fleischer, and A. H. Barr, "Analog VLSI implementation of gradient descent," in Adv. Neural Info. Proc. Syst. 5, S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann, 1993, pp. 789-796.
-
(1993)
Adv. Neural Info. Proc. Syst. 5
, pp. 789-796
-
-
Kirk, D.B.1
Kerns, D.2
Fleischer, K.3
Barr, A.H.4
-
48
-
-
0001848661
-
CMOS UV writeable non-volatile analog storage
-
Santa Cruz
-
D. A. Kerns, J. E. Tanner, M. A. Sivilotti, and J. Luo. "CMOS UV writeable non-volatile analog storage," in Advanced Research in VLSI, Santa Cruz, 1991, pp. 245-261.
-
(1991)
Advanced Research in VLSI
, pp. 245-261
-
-
Kerns, D.A.1
Tanner, J.E.2
Sivilotti, M.A.3
Luo, J.4
-
49
-
-
0026866964
-
Analysis and verification of an analog VLSI incremental outer product learning system
-
May
-
G. Cauwenberghs, C. F. Neugebauer, and A. Yariv, "Analysis and verification of an analog VLSI incremental outer product learning system." IEEE Trans. Neural Networks 3, pp. 488-497, May 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 488-497
-
-
Cauwenberghs, G.1
Neugebauer, C.F.2
Yariv, A.3
-
50
-
-
0027590004
-
UV activated conductances allow for multiple time-scale learning
-
May
-
R. G. Benson and D. A. Kerns, "UV activated conductances allow for multiple time-scale learning." IEEE Trans. Neural Networks 4, pp. 434-440, May 1993.
-
(1993)
IEEE Trans. Neural Networks
, vol.4
, pp. 434-440
-
-
Benson, R.G.1
Kerns, D.A.2
-
51
-
-
2342525058
-
A reconfigurable multichip analog neural network: Recognition and backpropagation training
-
Baltimore
-
S. Tam, M. Holler, J. Brauch, A. Pine, A. Peterson, S. Anderson, and S. Deiss, "A reconfigurable multichip analog neural network: Recognition and backpropagation training." Proc. IJCNN 92, Baltimore, Vol. 2, pp. 625-630, 1992.
-
(1992)
Proc. IJCNN 92
, vol.2
, pp. 625-630
-
-
Tam, S.1
Holler, M.2
Brauch, J.3
Pine, A.4
Peterson, A.5
Anderson, S.6
Deiss, S.7
-
52
-
-
0010545787
-
Relaxation networks for large supervised learning problems
-
D. S. Touretzky, J. Moody, and R. Lippmann, editors, Morgan Kaufmann: San Mateo, CA
-
J. Alspector, R. B. Allen, A. Jayakumar, T. Zeppenfeld, and R. Meir, "Relaxation networks for large supervised learning problems," in Adv. in Neural Info. Proc. Syst. 3, D. S. Touretzky, J. Moody, and R. Lippmann, editors, Morgan Kaufmann: San Mateo, CA, 1991, pp. 1015-1021.
-
(1991)
Adv. in Neural Info. Proc. Syst. 3
, pp. 1015-1021
-
-
Alspector, J.1
Allen, R.B.2
Jayakumar, A.3
Zeppenfeld, T.4
Meir, R.5
-
53
-
-
0041529468
-
Experimental evaluation of learning in a neural microsystem
-
Morgan Kaufmann: San Mateo, CA
-
J. Alspector, A. Jayakumar, and S. Luna, "Experimental evaluation of learning in a neural microsystem," in Advances in Neural Info. Proc. Syst. 4, Morgan Kaufmann: San Mateo, CA, 1992.
-
(1992)
Advances in Neural Info. Proc. Syst. 4
-
-
Alspector, J.1
Jayakumar, A.2
Luna, S.3
-
54
-
-
0023602192
-
A generic architecture for wafer scale neuromorphic systems
-
J. Raffel, J. Mann, R. Berger, A. Soares and S. Gilbert, "A generic architecture for wafer scale neuromorphic systems," in Proc. IEEE Int. Conf. Neural Networks III, 1987, pp. 501-513.
-
(1987)
Proc. IEEE Int. Conf. Neural Networks III
, pp. 501-513
-
-
Raffel, J.1
Mann, J.2
Berger, R.3
Soares, A.4
Gilbert, S.5
-
55
-
-
0003979924
-
-
Addison-Wesley: Menlo Park, CA
-
J. Hertz, A. Krogh, and R. G. Palmer, Introduction to the Theory of Neural Computation, Addison-Wesley: Menlo Park, CA, 1991.
-
(1991)
Introduction to the Theory of Neural Computation
-
-
Hertz, J.1
Krogh, A.2
Palmer, R.G.3
-
57
-
-
0024123145
-
Adding a conscience to competitive learning
-
San Diego
-
D. DeSieno, "Adding a conscience to competitive learning," Proc. IEEE Int. Conf. Neural Networks, Vol. 1, pp. 117-124, San Diego, 1988.
-
(1988)
Proc. IEEE Int. Conf. Neural Networks
, vol.1
, pp. 117-124
-
-
DeSieno, D.1
-
58
-
-
0025507915
-
Neural networks for vector quantization of speech and images
-
Oct.
-
A. K. Krishnamurthy, S. C. Ahalt, D. E. Melton, and P. Chen, "Neural networks for vector quantization of speech and images." IEEE J. Sel. Areas in Commun. 8, pp. 1449-1457, Oct. 1990.
-
(1990)
IEEE J. Sel. Areas in Commun.
, vol.8
, pp. 1449-1457
-
-
Krishnamurthy, A.K.1
Ahalt, S.C.2
Melton, D.E.3
Chen, P.4
-
59
-
-
0001031001
-
Winner-take-all networks of O(N) complexity
-
D. S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA
-
J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, "Winner-take-all networks of O(N) complexity," in Adv. in Neural Info. Proc. Syst. I, D. S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA, 1989, pp. 703-711.
-
(1989)
Adv. in Neural Info. Proc. Syst. I
, pp. 703-711
-
-
Lazzaro, J.1
Ryckebusch, S.2
Mahowald, M.A.3
Mead, C.A.4
-
60
-
-
0027590834
-
A high precision VLSI winner take all circuit for self-organizing neural networks
-
May
-
J. Choi and B. J. Sheu, "A high precision VLSI winner take all circuit for self-organizing neural networks." IEEE J. Solid St. Ccts. 28, pp. 576-584, May 1993.
-
(1993)
IEEE J. Solid St. Ccts.
, vol.28
, pp. 576-584
-
-
Choi, J.1
Sheu, B.J.2
-
61
-
-
0026866963
-
A VLSI neural processor for image data compression using self-organizing networks
-
May
-
W. C. Fang, B. J. Sheu, O. T. C. Chen, and J. Choi, "A VLSI neural processor for image data compression using self-organizing networks." IEEE Trans. Neural Networks 3, pp. 506-518, May 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 506-518
-
-
Fang, W.C.1
Sheu, B.J.2
Chen, O.T.C.3
Choi, J.4
-
63
-
-
2342584563
-
Criteria for robust stability in a class of lateral inhibition networks coupled through resistive grids
-
J. L. Wyatt and D. L. Standley, "Criteria for robust stability in a class of lateral inhibition networks coupled through resistive grids." Neural Computation 1, pp. 58-67, 1989.
-
(1989)
Neural Computation
, vol.1
, pp. 58-67
-
-
Wyatt, J.L.1
Standley, D.L.2
-
64
-
-
0004787812
-
An analog self-organizing neural network chip
-
D.S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA
-
J. R. Mann and S. Gilbert, "An analog self-organizing neural network chip," in Advances in Neural Information Processing Systems I, D.S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA, 1990, pp. 739-747.
-
(1990)
Advances in Neural Information Processing Systems I
, pp. 739-747
-
-
Mann, J.R.1
Gilbert, S.2
-
65
-
-
0023389776
-
Switched capacitor neural networks
-
Y. P. Tsividis and D. Anastassiou, "Switched capacitor neural networks." Elect. Lett. 23, pp. 958-959, 1987.
-
(1987)
Elect. Lett.
, vol.23
, pp. 958-959
-
-
Tsividis, Y.P.1
Anastassiou, D.2
-
66
-
-
0011781030
-
Pulse firing neural chips for hundreds of neurons
-
D. S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA
-
M. Brownlow, L. Tarassenko, A. F. Murray, A. Hamilton, S. Han and H. M. Reekie, "Pulse firing neural chips for hundreds of neurons," in Advances in Neural Information Processing Systems 2, D. S. Touretzky, editor, Morgan Kaufmann: San Mateo, CA, 1989, pp. 785-792.
-
(1989)
Advances in Neural Information Processing Systems
, vol.2
, pp. 785-792
-
-
Brownlow, M.1
Tarassenko, L.2
Murray, A.F.3
Hamilton, A.4
Han, S.5
Reekie, H.M.6
-
67
-
-
0025401319
-
Nonlinear switched capacitor neural networks for optimization problems
-
Mar.
-
A. Rodriguez-Vazquez, R. Dominguez-Castro, A. Rueda, J. L. Huertas, and E. Sanchez-Sinencio, "Nonlinear switched capacitor neural networks for optimization problems." IEEE Trans. Ccts. Systems 37, pp. 384-398, Mar. 1990.
-
(1990)
IEEE Trans. Ccts. Systems
, vol.37
, pp. 384-398
-
-
Rodriguez-Vazquez, A.1
Dominguez-Castro, R.2
Rueda, A.3
Huertas, J.L.4
Sanchez-Sinencio, E.5
-
68
-
-
0025628243
-
A switched capacitor bidirectional associative memory
-
B. Maundy and E. El-Masry, "A switched capacitor bidirectional associative memory." IEEE Trans. Ccts. and Systems 37, pp. 1568-1572, 1990.
-
(1990)
IEEE Trans. Ccts. and Systems
, vol.37
, pp. 1568-1572
-
-
Maundy, B.1
El-Masry, E.2
-
69
-
-
0026370879
-
A self organizing switched capacitor neural network
-
B. Maundy and E. El-Masry, "A self organizing switched capacitor neural network." IEEE Trans. Ccts. and Systems 38. pp. 1556-1563, 1991.
-
(1991)
IEEE Trans. Ccts. and Systems
, vol.38
, pp. 1556-1563
-
-
Maundy, B.1
El-Masry, E.2
-
70
-
-
2342570778
-
Analog CMOS neural circuits - In situ learning
-
H. C. Card and C. R. Schneider, "Analog CMOS neural circuits - In situ learning." Int. J. Neural Syst. 3, pp. 103-124, 1992.
-
(1992)
Int. J. Neural Syst.
, vol.3
, pp. 103-124
-
-
Card, H.C.1
Schneider, C.R.2
-
71
-
-
0026866360
-
A modular T-mode design approach for analog neural network hardware implementations
-
R. Linares-Barranco, E. Sanchez-Sinencio, A. Rodriguez-Vazquez, and J. L. Huertas, "A modular T-mode design approach for analog neural network hardware implementations." IEEE J. Solid St. Ccts. 27, pp. 701-713, 1992.
-
(1992)
IEEE J. Solid St. Ccts.
, vol.27
, pp. 701-713
-
-
Linares-Barranco, R.1
Sanchez-Sinencio, E.2
Rodriguez-Vazquez, A.3
Huertas, J.L.4
-
72
-
-
0000672424
-
Fast learning in networks of locally tuned processing units
-
J. Moody and C. J. Darken, "Fast learning in networks of locally tuned processing units." Neural Computation 1, pp. 281-294, 1989.
-
(1989)
Neural Computation
, vol.1
, pp. 281-294
-
-
Moody, J.1
Darken, C.J.2
-
74
-
-
0010547899
-
The bootstrap Widrow-Hoff rule as a cluster formation algorithm
-
G. E. Hinton and S. J. Nowlan, "The bootstrap Widrow-Hoff rule as a cluster formation algorithm." Neural Computation 2, pp. 355-362, 1990.
-
(1990)
Neural Computation
, vol.2
, pp. 355-362
-
-
Hinton, G.E.1
Nowlan, S.J.2
-
75
-
-
0010543919
-
-
Information Technology Research Center, University of Toronto
-
G. E. Hinton, Neural Networks for Industry. Information Technology Research Center, University of Toronto, 1991.
-
(1991)
Neural Networks for Industry
-
-
Hinton, G.E.1
-
76
-
-
0002629270
-
Maximum likelihood from incomplete data via the EM algorithm
-
A. P. Dempster, N. M. Laird, and D. B. Rubin, "Maximum likelihood from incomplete data via the EM algorithm." J. Royl Sta. Soc. 39, pp. 1-38, 1977.
-
(1977)
J. Royl Sta. Soc.
, vol.39
, pp. 1-38
-
-
Dempster, A.P.1
Laird, N.M.2
Rubin, D.B.3
-
77
-
-
0002399288
-
Neural networks, principal components, and subspaces
-
E. Oja, "Neural networks, principal components, and subspaces." Int. J. Neural Systems 1, pp. 61-68, 1989.
-
(1989)
Int. J. Neural Systems
, vol.1
, pp. 61-68
-
-
Oja, E.1
-
79
-
-
0001457509
-
Some methods for classification and analysis of multivariate data
-
University of California Press
-
J. MacQueen, "Some methods for classification and analysis of multivariate data," in Proc. 5th Berkeley Symp. on Prob. and Statistics, University of California Press, 1967.
-
(1967)
Proc. 5th Berkeley Symp. on Prob. and Statistics
-
-
MacQueen, J.1
-
80
-
-
0027634778
-
Generalized clustering networks and Kohonen's self-organizing scheme
-
July
-
N. R. Pal, J. C. Bezdek, and E. C. K. Tsao, "Generalized clustering networks and Kohonen's self-organizing scheme." IEEE Trans. Neural Networks 4, pp. 549-557, July 1993.
-
(1993)
IEEE Trans. Neural Networks
, vol.4
, pp. 549-557
-
-
Pal, N.R.1
Bezdek, J.C.2
Tsao, E.C.K.3
-
81
-
-
0021776661
-
A massively parallel architecture for a self-organizing neural pattern recognition machine
-
G. A. Carpenter and S. Grossberg, "A massively parallel architecture for a self-organizing neural pattern recognition machine." Computer Vision, Graphics and Image Processing 37, pp. 54-115, 1987.
-
(1987)
Computer Vision, Graphics and Image Processing
, vol.37
, pp. 54-115
-
-
Carpenter, G.A.1
Grossberg, S.2
-
82
-
-
0023981451
-
The ART of adaptive pattern recognition by a self-organizing neural network
-
Mar.
-
G. A. Carpenter and S. Grossberg, "The ART of adaptive pattern recognition by a self-organizing neural network." IEEE Computer, pp. 77-88, Mar. 1988.
-
(1988)
IEEE Computer
, pp. 77-88
-
-
Carpenter, G.A.1
Grossberg, S.2
-
83
-
-
0942280595
-
A self-organizing neural network for supervised learning, recognition, and prediction
-
Sept.
-
G. A. Carpenter and S. Grossberg, "A self-organizing neural network for supervised learning, recognition, and prediction." IEEE Commun. Mag. pp. 38-49, Sept. 1992.
-
(1992)
IEEE Commun. Mag.
, pp. 38-49
-
-
Carpenter, G.A.1
Grossberg, S.2
-
84
-
-
84899925703
-
A radial basis function neurocomputer implemented with analog VLSI circuits
-
Baltimore
-
S. S. Watkins and P. M. Chau, "A radial basis function neurocomputer implemented with analog VLSI circuits," Proc. IJCNN 92, Baltimore, 1992, Vol. 2, pp. 607-612.
-
(1992)
Proc. IJCNN 92
, vol.2
, pp. 607-612
-
-
Watkins, S.S.1
Chau, P.M.2
-
85
-
-
0242675517
-
An analog VLSI chip for radial basis functions
-
S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann
-
J. Anderson, J. C. Platt, and D. B. Kirk, "An analog VLSI chip for radial basis functions," in Adv. Neural Info. Proc. Syst. 5, S. J. Hanson, J. D. Cowan, and C. L. Giles, editors, Morgan Kaufmann, 1993, pp. 765-772.
-
(1993)
Adv. Neural Info. Proc. Syst. 5
, pp. 765-772
-
-
Anderson, J.1
Platt, J.C.2
Kirk, D.B.3
-
86
-
-
0026373253
-
Bump circuits for computing similarity and dissimilarity of analog voltages
-
Seattle, July
-
T. Delbruck, "Bump circuits for computing similarity and dissimilarity of analog voltages," in Proc. Int. Joint Conf. on Neural Networks, Seattle, July 1991, Vol. 1, pp. 475-479.
-
(1991)
Proc. Int. Joint Conf. on Neural Networks
, vol.1
, pp. 475-479
-
-
Delbruck, T.1
-
87
-
-
84941493307
-
An analog VLSI splining circuit
-
D. S. Touretzky, J. Moody, and R. Lippmann, editors, Morgan Kaufmann: San Mateo, CA, Apr.
-
D. B. Schwartz and V. K. Samalam, "An analog VLSI splining circuit," in Advances in Neural Information Processing Systems 3, D. S. Touretzky, J. Moody, and R. Lippmann, editors, Morgan Kaufmann: San Mateo, CA, Apr. 1991, pp. 1008-1014.
-
(1991)
Advances in Neural Information Processing Systems 3
, pp. 1008-1014
-
-
Schwartz, D.B.1
Samalam, V.K.2
-
88
-
-
0026853615
-
MOS circuit for nonlinear Hebbian learning
-
M. H. Cohen and A. C. Andreou, "MOS circuit for nonlinear Hebbian learning." Elect. Lett. 28, pp. 591-593, 1992.
-
(1992)
Elect. Lett.
, vol.28
, pp. 591-593
-
-
Cohen, M.H.1
Andreou, A.C.2
-
89
-
-
0026866246
-
Current mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network
-
M. H. Cohen and A. G. Andreou, "Current mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network." IEEE J. Solid St. Ccts. 27, pp. 714-723, 1992.
-
(1992)
IEEE J. Solid St. Ccts.
, vol.27
, pp. 714-723
-
-
Cohen, M.H.1
Andreou, A.G.2
-
90
-
-
2342507568
-
CMOS integration of Herault-Jutten cells for separation of sources
-
C. A. Mead and M. Ismail, editors, Kluwer: Boston
-
E. Vittoz and X. Arreguit, "CMOS integration of Herault-Jutten cells for separation of sources," in Analog VLSI Implementation of Neural Systems, C. A. Mead and M. Ismail, editors, Kluwer: Boston, 1989, pp. 57-83.
-
(1989)
Analog VLSI Implementation of Neural Systems
, pp. 57-83
-
-
Vittoz, E.1
Arreguit, X.2
-
93
-
-
84940109925
-
Analog VLSI implementation of a Kohonen map
-
Lausanne, Oct.
-
E. Vittoz, E. Sorouchyari, P. Heim, X. Arreguit, and F. Krummenacher, "Analog VLSI implementation of a Kohonen map," in Proc. Journees D'Electronique 1989, Lausanne, Oct. 1989, pp. 292-301.
-
(1989)
Proc. Journees D'Electronique 1989
, pp. 292-301
-
-
Vittoz, E.1
Sorouchyari, E.2
Heim, P.3
Arreguit, X.4
Krummenacher, F.5
-
94
-
-
0025721267
-
Generation of learning neighbourhood in Kohonen feature maps by means of simple nonlinear network
-
P. Heim, B. Hochet, and E. Vittoz, "Generation of learning neighbourhood in Kohonen feature maps by means of simple nonlinear network." Elect. Lett. 27, pp. 275-277, 1991.
-
(1991)
Elect. Lett.
, vol.27
, pp. 275-277
-
-
Heim, P.1
Hochet, B.2
Vittoz, E.3
-
95
-
-
0026123818
-
Implementation of a learning Kohonen neuron based on a new multilevel storage technique
-
Mar.
-
B. Hochet, V. Peiris, S. Abdo, and M. J. Declercq, "Implementation of a learning Kohonen neuron based on a new multilevel storage technique." IEEE J. Solid St. Ccts. 26, pp. 262-267, Mar. 1991.
-
(1991)
IEEE J. Solid St. Ccts.
, vol.26
, pp. 262-267
-
-
Hochet, B.1
Peiris, V.2
Abdo, S.3
Declercq, M.J.4
-
96
-
-
0026817590
-
CMOS self-biased Euclidean distance computing circuit with high dynamic range
-
O. Landolt, E. Vittoz, and P. Heim, "CMOS self-biased Euclidean distance computing circuit with high dynamic range." Elect. Lett. 28, pp. 352-354, 1992.
-
(1992)
Elect. Lett.
, vol.28
, pp. 352-354
-
-
Landolt, O.1
Vittoz, E.2
Heim, P.3
-
97
-
-
0027594068
-
Analog implementation of a Kohonen map with on-chip learning
-
May
-
D. Macq, M. Verleysen, P. Jespers, and J. D. Legat, "Analog implementation of a Kohonen map with on-chip learning." IEEE Trans. Neural Networks 4, pp. 456-461, May 1993.
-
(1993)
IEEE Trans. Neural Networks
, vol.4
, pp. 456-461
-
-
Macq, D.1
Verleysen, M.2
Jespers, P.3
Legat, J.D.4
-
98
-
-
0027594584
-
A charge-based on-chip adaptation Kohonen neural network
-
May
-
Y. He and U. Cilingiroglu, "A charge-based on-chip adaptation Kohonen neural network." IEEE Trans. Neural Networks 4, pp. 462-469, May 1993.
-
(1993)
IEEE Trans. Neural Networks
, vol.4
, pp. 462-469
-
-
He, Y.1
Cilingiroglu, U.2
-
99
-
-
0028732519
-
Implementation of a fully parallel Kohonen map: A mixed analog digital approach
-
V. Peiris, B. Hochet, and M. Declercq, "Implementation of a fully parallel Kohonen map: A mixed analog digital approach." Proc. ICNN 4, pp. 2064-2069, 1994.
-
(1994)
Proc. ICNN
, vol.4
, pp. 2064-2069
-
-
Peiris, V.1
Hochet, B.2
Declercq, M.3
-
100
-
-
0028425063
-
Quantization effects in digitally behaving circuit implementations of Kohonen networks
-
May
-
P. Thiran, V. Peiris, P. Heim, and B. Hochet, "Quantization effects in digitally behaving circuit implementations of Kohonen networks." IEEE Trans. NNs 5, pp. 450-458, May 1994.
-
(1994)
IEEE Trans. NNs
, vol.5
, pp. 450-458
-
-
Thiran, P.1
Peiris, V.2
Heim, P.3
Hochet, B.4
-
101
-
-
77956004588
-
An analog CMOS implementation of a Kohonen network with learning capability
-
J. G. Delgado-Frias and W. R. Moore, editors, Plenum Press: New York
-
O. Landolt, "An analog CMOS implementation of a Kohonen network with learning capability," in VLSI for Neural Networks and Artificial Intelligence, J. G. Delgado-Frias and W. R. Moore, editors, Plenum Press: New York, 1994, pp. 25-34.
-
(1994)
VLSI for Neural Networks and Artificial Intelligence
, pp. 25-34
-
-
Landolt, O.1
-
102
-
-
0028429267
-
A communication architecture tailored for analog VLSI artificial neural networks: Intrinsic performance and limitations
-
May
-
A. Mortara and E. Vittoz, "A communication architecture tailored for analog VLSI artificial neural networks: Intrinsic performance and limitations." IEEE Trans. Neural Networks 5, pp. 549-466, May 1994.
-
(1994)
IEEE Trans. Neural Networks
, vol.5
, pp. 549-1466
-
-
Mortara, A.1
Vittoz, E.2
-
103
-
-
0026897288
-
Resistive grid image filtering: Input/output analysis via the CNN framework
-
B. E. Shi and L. O. Chua, "Resistive grid image filtering: Input/output analysis via the CNN framework." IEEE Trans. Ccts. and Syst. I: Fund. Th. and Appl. 39, pp. 531-548, 1992.
-
(1992)
IEEE Trans. Ccts. and Syst. I: Fund. Th. and Appl.
, vol.39
, pp. 531-548
-
-
Shi, B.E.1
Chua, L.O.2
-
104
-
-
0026866737
-
An analog implementation of discrete time cellular neural networks
-
May
-
H. Harrer, J. A. Nossek, and R. Stelzl, "An analog implementation of discrete time cellular neural networks." IEEE Trans. Neural Networks 3, pp. 466-476, May 1992.
-
(1992)
IEEE Trans. Neural Networks
, vol.3
, pp. 466-476
-
-
Harrer, H.1
Nossek, J.A.2
Stelzl, R.3
-
105
-
-
0029178533
-
The impact of VLSI fabrication on neural learning
-
Seattle
-
H. C. Card, D. K. McNeill, C. R. Schneider and R. S. Schneider, "The impact of VLSI fabrication on neural learning," in Proc. IEEE ISCAS, Seattle, 1995, Vol. 2, pp. 985-988.
-
(1995)
Proc. IEEE ISCAS
, vol.2
, pp. 985-988
-
-
Card, H.C.1
McNeill, D.K.2
Schneider, C.R.3
Schneider, R.S.4
-
106
-
-
0028748429
-
Analog hardware tolerance of soft competitive learning
-
Orlando
-
D. K. McNeill and H. C. Card, "Analog hardware tolerance of soft competitive learning," in Proc. IEEE ICNN, Orlando, 1994, Vol. 4, pp. 2004-2008.
-
(1994)
Proc. IEEE ICNN
, vol.4
, pp. 2004-2008
-
-
McNeill, D.K.1
Card, H.C.2
-
107
-
-
0022219187
-
Code-excited linear prediction (CELP); High quality speech at very low bit rates
-
M. R. Schroeder and B. S. Atal, "Code-excited linear prediction (CELP); High quality speech at very low bit rates," in Proc. IEEE Int. Conf. Acoust., Speech, and Signal Processing, 1985, pp. 937-940.
-
(1985)
Proc. IEEE Int. Conf. Acoust., Speech, and Signal Processing
, pp. 937-940
-
-
Schroeder, M.R.1
Atal, B.S.2
-
110
-
-
0010546986
-
Limited-precision unsupervised learning algorithms for speech coding
-
Washington, D.C., July
-
S. Kamarsu and H. C. Card, "Limited-precision unsupervised learning algorithms for speech coding," in Proc. INNS World Congress on Neural Networks, Washington, D.C., July 1995, Vol. 1, pp. 128-131.
-
(1995)
Proc. INNS World Congress on Neural Networks
, vol.1
, pp. 128-131
-
-
Kamarsu, S.1
Card, H.C.2
-
111
-
-
0025505430
-
Adaptive vector quantization using a self-development neural network
-
Oct.
-
T. C. Lee and A. M. Peterson, "Adaptive vector quantization using a self-development neural network." IEEE J. Sel. Areas in Commun. 8, pp. 1458-1471, Oct. 1990.
-
(1990)
IEEE J. Sel. Areas in Commun.
, vol.8
, pp. 1458-1471
-
-
Lee, T.C.1
Peterson, A.M.2
-
112
-
-
0027583348
-
Adaptive speech coding with DCT and neural net vector quantization
-
Apr.
-
L. V. Veleva and R. K. Kunchev, "Adaptive speech coding with DCT and neural net vector quantization." Elect. Lett. 29, pp. 704-705, Apr. 1993.
-
(1993)
Elect. Lett.
, vol.29
, pp. 704-705
-
-
Veleva, L.V.1
Kunchev, R.K.2
-
113
-
-
0010581971
-
-
MSc. thesis, Dept. of Electrical and Computer Engineering, University of Manitoba
-
B. Frey, "Code and wavelet excited linear prediction of speech," MSc. thesis, Dept. of Electrical and Computer Engineering, University of Manitoba, 1994.
-
(1994)
Code and Wavelet Excited Linear Prediction of Speech
-
-
Frey, B.1
|