Cofired bump bonding technique for chip scale package fabrication using zero X-Y shrinkage low temperature cofired ceramic substrate

International Journal of Microcircuits and Electronic Packaging

Volumn 21, Issue 1, 1998, Pages 46-51

  Itagaki, Minehiro ^a   Hase, Nobuhiro ^a   Yuhaku, Satoru ^a   Bessho, Yoshihiro ^a   Eda, Kazuo ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESIVES; BOND STRENGTH (MATERIALS); BONDING; CERAMIC MATERIALS; CONDUCTIVE MATERIALS; FABRICATION; LSI CIRCUITS; SOLDERING; SUBSTRATES;

CHIP SCALE PACKAGES; COFIRED BUMP BONDING TECHNIQUE; ZERO X Y SHRINKAGE LOW TEMPERATURE COFIRED CERAMIC SUBSTRATES;

ELECTRONICS PACKAGING;

EID: 0032010275     PISSN: 10631674     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (10)