Molded chip scale package for high pin count

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 21, Issue 1, 1998, Pages 28-34

  Baba, Shinji ^a   Tomita, Yoshihiro ^a   Matsuo, Mitsuyasu ^a   Matsushima, Hironori ^a   Ueda, Naoto ^a   Nakagawa, Osamu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Chip scale package; Known good die; Robust package; Screen printing; Solder bumping; Transfer molding; Wiring conductor pattern

Indexed keywords

ELECTRIC WIRING; INTEGRATED CIRCUIT MANUFACTURE; LSI CIRCUITS; PRINTED CIRCUIT BOARDS; SCREEN PRINTING; SOLDERING; TRANSFER MOLDING;

CHIP SCALE PACKAGE (CSP); SOLDER BUMPING; WIRING CONDUCTOR PATTERNS;

ELECTRONICS PACKAGING;

EID: 0032002770     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.659503     Document Type: Article

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