Shared memory implementation of a parallel switch-level circuit simulator

Proceedings of the Workshop on Parallel and Distributed Simulation, PADS

Volumn , Issue , 1998, Pages 134-141

  Chen, Yu an ^a   Bagrodia, Rajive ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; DATA STORAGE EQUIPMENT; ELECTRIC NETWORK ANALYSIS; NETWORK PROTOCOLS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

PARALLEL SWITCH LEVEL CIRCUIT SIMULATORS; SHARED MEMORY MULTIPROCESSOR ARCHITECTURE;

COMPUTER SIMULATION;

EID: 0031701224     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/278009.278025     Document Type: Conference Paper

References (19)