HIPIQS: A high-performance switch architecture using input queuing

Proceedings of the International Parallel Processing Symposium, IPPS

Volumn , Issue , 1998, Pages 134-143

  Sivaram, Rajeev ^a   Stunkel, Craig B ^a   Panda, Dhabaleswar K ^a  

^a OHIO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); DATA COMMUNICATION SYSTEMS; LOCAL AREA NETWORKS; PARALLEL PROCESSING SYSTEMS; QUEUEING THEORY; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC; WIDE AREA NETWORKS;

HIGH PERFORMANCE INPUT QUEUED SWITCH (HIPIQS); SWITCHED BASED INTERCONNECTS;

INTERCONNECTION NETWORKS;

EID: 0031698810     PISSN: 10637133     EISSN: None     Source Type: None    
DOI: 10.1109/IPPS.1998.669901     Document Type: Conference Paper

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