Effective capacitance macro-modelling for architectural-level power estimation

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1998, Pages 414-419

  Khellah, Muhammad M ^a   Elmasry, M I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; MACROS; MATHEMATICAL MODELS; MOSFET DEVICES;

ARCHITECTURAL LEVEL POWER ESTIMATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031698593     PISSN: 10661395     EISSN: None     Source Type: None    
DOI: 10.1109/GLSV.1998.665336     Document Type: Conference Paper

References (7)

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2. D. Singh Power Conscious CAD Tools and Methodologies: A Perspective Proc. of the IEEE 570 594 April 1995
3. A. Deng Power Analysis for CMOS/BiCMOS Circuits 1994 Int'l Workshop on Low Power Design 3 8 1994 Int'l Workshop on Low Power Design 1994
4. P. Landman J. Rabaey Black-Box Capacitance Models for Architectural Power Analysis International Workshop on Low Power Design 165 170 International Workshop on Low Power Design 1994-April
5. A. Raghunathan Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption ICCAD ICCAD 1996-Nov.
6. H. Mehta Energy Characterization Based on Clustering 33rd Design Automation Conference 702 707 33rd Design Automation Conference 1996
7. R. Burch A Monte Carlo Approach for Power Estimation IEEE Transactions on VLSI Systems 1 1 63 71 March 1993