How to transform an architectural synthesis tool for low power VLSI designs

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1998, Pages 426-431

  Gailhard, S ^a   Julien, N ^a   Diguet, J Ph ^a   Martin, E ^a  

^a LESTER UBS Lab   (France)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH LEVEL SYNTHESIS (HLS);

ALGORITHMS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031680372     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLSV.1998.665338     Document Type: Conference Paper

References (14)