Integrated memory/logic architecture for image processing

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 304-309

  Charles, G Sodini ^a   Gealow, Jeffrey C ^a   Talib, Zubair A ^a   Masaki, Ichiro ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; CELLULAR ARRAYS; IMAGE SEGMENTATION; INTERCONNECTION NETWORKS; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; SIGNAL FILTERING AND PREDICTION;

DYNAMIC RANDOM ACCESS MEMORY (DRAM); FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

INTEGRATED CIRCUIT LAYOUT;

EID: 0031678283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)