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Volumn 46, Issue 1, 1998, Pages 263-268

Memory efficient programmable processor chip for inverse haar transform

Author keywords

Digital signal processors; Haar transforms; Image processing; Transform coding; Very large scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; EFFICIENCY; IMAGE PROCESSING; MATHEMATICAL TRANSFORMATIONS; PERFORMANCE; VLSI CIRCUITS;

EID: 0031675437     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.651233     Document Type: Article
Times cited : (9)

References (11)
  • 3
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    • An efficient prime-factor algorithm for the discrete cosine transform and its hardware implementations
    • . 42, pp. 1996-2005, Aug. 1994.
    • P. Lee and F. HuangAn efficient prime-factor algorithm for the discrete cosine transform and its hardware implementationsIEEE Trans. Signal Processing, . 42, pp. 1996-2005, Aug. 1994.
    • IEEE Trans. Signal Processing
    • Lee, P.1    Huang, F.2
  • 4
    • 0028410099 scopus 로고    scopus 로고
    • On the real-time computation of DFT and DCT through systolic architectures
    • . 42, pp. 988-991, Aug. 1994.
    • N. R. Murthy and M. N. S. SwamyOn the real-time computation of DFT and DCT through systolic architecturesIEEE Trans. Signal Processing, . 42, pp. 988-991, Aug. 1994.
    • IEEE Trans. Signal Processing
    • Murthy, N.R.1    Swamy, M.N.S.2
  • 6
    • 0025703419 scopus 로고    scopus 로고
    • VLSI computing architectures for Haar transform
    • . 26, no. 23, pp. 1962-1963, Nov. 1990.
    • K. J. R. LiuVLSI computing architectures for Haar transformElectron. Lett., . 26, no. 23, pp. 1962-1963, Nov. 1990.
    • Electron. Lett.
    • Liu, K.J.R.1
  • 8
    • 33747810683 scopus 로고    scopus 로고
    • A three processor parallel-pipelined architecture of the 2D-FHT at video rates
    • 1SMM/1ASTED Int. Conf. Parallel Distributed Comput. Syst., Washington, DC, Oct. 1991, pp. 170-174.
    • J. A. Michell, A. M. Burön, J. M. Solana, and G. RuizA three processor parallel-pipelined architecture of the 2D-FHT at video ratesProc. Fourth 1SMM/1ASTED Int. Conf. Parallel Distributed Comput. Syst., Washington, DC, Oct. 1991, pp. 170-174.
    • Proc. Fourth
    • Michell, J.A.1    Burön, A.M.2    Solana, J.M.3    Ruiz, G.4
  • 9
    • 0001175630 scopus 로고    scopus 로고
    • A high speed Haar transform implementation
    • . 2, no. 3, pp. 207-226, 1992.
    • M. G. Albanesi and M. FerretiA high speed Haar transform implementationJ. Circuits, Syst. Comput, . 2, no. 3, pp. 207-226, 1992.
    • J. Circuits, Syst. Comput
    • Albanesi, M.G.1    Ferreti, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.