A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

IEEE Electron Device Letters

Volumn 19, Issue 1, 1998, Pages 26-28

  Lin, Horng Chih ^a,b   Lin, Raymond ^b   Wu, Wen Fa ^b   Yang, Rong Ping ^b   Tsai, Ming Shih ^b   Chao, Tien Sheng ^a,b   Huang, Tiao Yuan ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; ELECTRODES; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; THERMODYNAMIC STABILITY; VLSI CIRCUITS;

OPTICAL STEPPER; PARASITIC GATE RESISTANCE; T SHAPED GATE ELECTRODE;

MOSFET DEVICES;

EID: 0031673753     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.650343     Document Type: Article

References (11)

1. B. Davari. W. H. Chang, K. E. Petrilio, C. Y. Wong, D. Moy, Y. Taur, M. R. Wordeman, J. Y.-C. Sun, C. C.-H. Hsu, and M. R. Polcari, "A high-performance 0.25-mm CMOS technology: II - Technology." IEEE Trans. Electron Devices, vol 39, pp. 967-974, 1992.
2. K. Fuji, K. Kikuta, and K. Kikkawa, "Sub-quarter-micron Ti salicide technology with in situ silicidation using high-temperature sputtering." in VLSI Tech. Dig., 1995, pp. 57-58.
3. K. Inoue, K. Mikagi, H. Abiko, and T. Kikkawa. "A new cobalt salicide technology for 0.15-μm CMOS using high-temperature sputtering and in situ vacuum annealing." IEDM Tech. Dig., 1995. pp. 445-448.
4. 2 salicide CMOS technology thermally stable up to 1000 °C with high TDDB reliability," in VLSI Tech. Dig., 1997, pp. 101-102.
5. J. A. Kittl, Q. Z. Hong, M. Rodder, D. A. Prinslow, and G. R, Misium, "A Ti salicide process for 0.1-mm gate length CMOS technology." in VLSI Tech. Dig., 1996, pp. 14-15.
6. J. A. Kittl, Q. Z. Hong, C. P. Chao, I. C. Chen, S. O'Brien, and M. Hanratty, "Salicides for 0.1-μm gate lengths: A comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization, and Co processes," in VLSI Tech. Dig., 1997, pp. 103-104.
7. Y. Nitta, T. Ohshima, R. Shigemasa, S. Nishi, and T. Kimura, "Control of electro-chemical etching for uniform 0.1-μm gate formation of HEMT." in IEDM Tech. Dig., 1996, pp. 47-50.
8. T. Tanaka, H. Furukawa, H. Takenaka, T. Ueda, T. Fukui, and D. Ueda, "Low-voltage operation GaAs spike-gate power FET with high-power-added efficiency." IEEE Trans. Electron Devices, vol. 44. pp. 354-359. 1997.
9. D. Hisamoto, K. Umeda, Y. Nakamura, and S. Kimura, "A low resistance self-aligned T-shaped gate for high-performance sub-0.l-μm CMOS." IEEE Trans. Electron Devices. vol. 44, pp. 951-956, 1997.
10. D. Y. Jeon, G. M. Chin, K. F. Lee, R. H. Yan, E. Westrwick, and M. Cerullo. "Gate technology for 0.1-μm Si CMOS using g-line and deep UV hardening." J. Vac. Sci. Technol., vol. B12, pp. 2800-2840, 1994.
11. 2." IEEE Trans. Electron Devices, vol. 38, pp. 262-269, 1991.