Integrating online and offline testing of a switching memory

IEEE Design and Test of Computers

Volumn 15, Issue 1, 1998, Pages 63-70

  Barbagallo, Stefano ^a,c,d,e,f   Medina, Davide ^a,b,c,e   Corno, Fulvio ^b,e   Prinetto, Paolo ^b,e   Reorda, Matteo Sonza ^b  

^a Ltaltel ^*  (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c Italtel's Ctrl R and D Labs   (Italy)

^d POLITECNICO DI MILANO   (Italy)

^e IEEE

^f Italtel SpA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; ONLINE SYSTEMS; RANDOM ACCESS STORAGE; SHIFT REGISTERS; TELEPHONE SWITCHING EQUIPMENT; USER INTERFACES;

BOUNDARY SCAN TESTING; BUILT IN SELF TEST (BIST); OFFLINE TESTING; ONLINE TESTING; PARTIAL SCAN TESTING; SWITCHING MEMORY CIRCUITS (SMC);

SWITCHING CIRCUITS;

EID: 0031655150     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.655184     Document Type: Article

References (7)

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