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Volumn , Issue , 1998, Pages 70-75
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Behavioral emulation of synthesized RT-level descriptions using VLIW architectures
a a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
CODES (SYMBOLS);
FINITE AUTOMATA;
MICROPROCESSOR CHIPS;
SEQUENTIAL MACHINES;
BEHAVIORAL EMULATION;
VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURES;
COMPUTER ARCHITECTURE;
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EID: 0031655007
PISSN: 10746005
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (3)
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References (13)
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