VLSI ATM switch architecture for VBR traffic

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 420-427

  Ranganathan, N ^a   Anand, Rajat ^a   Chiruvolu, Girish ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BUFFER CIRCUITS; BUFFER STORAGE; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; PACKET SWITCHING; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

CENTRAL BUFFER SWITCH; DYNAMIC MEMORY ALLOCATION; VARIABLE BIT RATE (VBR);

SWITCHING NETWORKS;

EID: 0031651854     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)