Low power SRAM using auto-backgate-controlled MT-CMOS

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages

  Nii, Koji ^a   Makino, Hiroshi ^a   Tujihashi, Yoshiki ^a   Morishima, Chikayoshi ^a   Hayakawa, Yasushi ^a   Nunogami, Hiroyuki ^a   Arakawa, Takahiko ^a   Hamano, Hisanori ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS;

MULTI THRESHOLD-COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (MT-CMOS); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031645889     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)