Cheap and easy systematic CMOS transistor mismatch characterization

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 466-469

  Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabe ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; COMPUTER SOFTWARE; CORRELATION METHODS; ELECTRIC NETWORK ANALYSIS; FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RANDOM PROCESSES;

MISMATCH CHARACTERIZATION CHIPS; SOFTWARE PACKAGE HSPICE;

MOSFET DEVICES;

EID: 0031645542     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)