The DT-model: High-level synthesis using data transfers

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 114-117

  Tarafdar, Shantanu ^a   Leeser, Miriam ^a  

^a Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; DATA TRANSFER; DIGITAL STORAGE; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; RESOURCE ALLOCATION;

EXECUTION UNITS; HLS SYSTEM; STORAGE ARCHITECTURES; SUB-PROBLEMS; TRANSFER MODELS;

HIGH LEVEL SYNTHESIS; COMPUTER AIDED DESIGN;

HIGH-LEVEL SYNTHESIS;

EID: 0031645158     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. D. Laneer, M. Cornero, G. Goosens, and H. De Man. Data Routing: A Paradigm for Efficient Data-Path Synthesis and Code Generation. Proceedings of the 7th International Symposium on High Level Synthesis, pages 17-22, 1994.
3. H. D. Lee and S.-Y. Hwang. A scheduling algorithm for multiport memory minimization in datapath synthesis. Proceedings of the ASP-DAC'95/GHDL'95/VLSI'95, pages 93-100, 1995.
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5. S. Tarafdar. A Data-Transfer Model For High Level Synthesis And Its Application In Storage And Interconnect Optimization. PhD thesis, Cornell University, 1998.
6. C.-Y. Wang and K. K. Parhi. High-Level DSP Synthesis Using Concurrent Transformations, Scheduling, and Allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(3):274-295, March 1995.