Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 215-220

  Chung, Ki Seok ^a   Liu, C L ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; ELECTRIC NETWORK SYNTHESIS; ENERGY UTILIZATION; OPTIMIZATION; PERTURBATION TECHNIQUES;

LOCAL TRANSFORMATION TECHNIQUES; LOGIC PERTURBATION; MULTI LEVEL COMBINATIONAL LOGIC SYNTHESIS;

LOGIC CIRCUITS;

EID: 0031644941     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)