Empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages

  Gebotys, Catherine H ^a   Gebotys, Robert J ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; MATHEMATICAL MODELS; STATISTICAL METHODS;

POWER PREDICTION MODELS;

MICROPROCESSOR CHIPS;

EID: 0031644258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/280756.280824     Document Type: Conference Paper

References (8)