Bipartitioning circuits using TABU search

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1998, Pages 223-227

  Lodha, Sandeep K ^a   Bhatia, Dinesh ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; GRAPH THEORY; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

ELECTRICAL CIRCUIT BIPARTITIONING;

ELECTRIC NETWORK SYNTHESIS;

EID: 0031644253     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)