Novel air gap integration scheme for multi-level interconnects using self-aligned via plugs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 46-47

  Ueda, Tetsuya ^a   Tamaoka, Eiji ^a   Yamashita, Kyoji ^a   Aoi, Nobuo ^a   Mayumi, Shuichi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; PERMITTIVITY; SEMICONDUCTOR DEVICE STRUCTURES;

AIR GAP INTEGRATION SCHEME;

ULSI CIRCUITS;

EID: 0031644052     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)