CMOS current-mode pipeline ADC using zero-voltage sampling technique

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1998, Pages 9-12

  Hui, Ronny C C ^a   Luong, Howard C ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; ENERGY UTILIZATION; ERROR CORRECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS;

REGULATED CASCODE CIRCUITS; SAMPLE-AND-HOLD CIRCUITS; ZERO-VOLTAGE SAMPLING TECHNIQUES;

ANALOG TO DIGITAL CONVERSION;

EID: 0031642675     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)