16-Bit parallel MAC architecture for a multimedia RISC processor

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1998, Pages 103-112

  Kuroda, Ichiro ^a   Murata, Eri ^a   Nadehara, Kouhei ^a   Suzuki, Kazumasa ^a   Arai, Tomohisa ^a   Okamura, Atsushi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; DATA TRANSFER; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS;

PARALLEL MULTIPLY-ACCUMULATION (MAC) ARCHITECTURES; SINGLE INSTRUCTION MULTIPLE DATA (SIMD); SYMMETRIC ROUNDING SCHEMES;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0031642614     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)