Digital demodulator matching on a FPGA

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 1998, Pages 366-375

  Boutillon, Emmanuel ^a   Danger, Jean Luc ^a   Fonseca, Lucie ^a   Garcia, Andres ^a   Gonzalez, Luis ^a  

^a TELECOM PARISTECH   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; LOGIC DEVICES;

DIGITAL DEMODULATORS;

DEMODULATORS;

EID: 0031642330     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)